https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/125351
>From c2b60a80a827f84ff7fcc18fbe8e98eca7f6e772 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Sat, 1 Feb 2025 18:21:24 +
Subject: [PATCH 1/2] [AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM
---
l
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/120557
>From 72fe9343aaaffb5e1f8f242def12a6ba0070b106 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 11 Feb 2025 12:36:40 +
Subject: [PATCH 1/5] [CodeGen][NewPM] Plug greedy RA in codegen pipeline
---
llv
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/127984
Making all reg alloc classes have an `::Option` class makes things nicer to
construct them.
>From fd718fac50a728bd4b5312689b64a2f519b1e27a Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 18 Feb 2025 04:
optimisan wrote:
* **#127984** (this)
* **#125351**
* **#120557**
* **#119540**
* **#118462**
* **#117309**
* **#119181**
* `main`
https://github.com/llvm/llvm-project/pull/127984
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/125351
>From 9c7ddfe1fd7b93bfa997bc595c7ba3056fa53534 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Sat, 1 Feb 2025 18:21:24 +
Subject: [PATCH 1/2] [AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM
---
l
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/127984
>From 254dabf793e4c6e7cc8a3aedbd8e093b88c583fa Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 18 Feb 2025 04:55:35 +
Subject: [PATCH] [RegAlloc][NPM] Make RegAllocFastPassOptions a nested class
Maki
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/128151
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/115434
>From 17ae43cbf8e8aad79f3cba192079c3841e1425f5 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 30 Oct 2024 04:56:54 +
Subject: [PATCH 1/4] [CodeGen][NewPM] Port MachineSink to NPM
Targets can set the
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/128151
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@@ -189,30 +198,19 @@ class MachineSinking : public MachineFunctionPass {
bool EnableSinkAndFold;
public:
- static char ID; // Pass identification
-
- MachineSinking() : MachineFunctionPass(ID) {
-initializeMachineSinkingPass(*PassRegistry::getPassRegistry());
- }
-
-
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/138829
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https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/138830
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optimisan wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/138829?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/138828
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@@ -279,6 +278,7 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
#ifndef DUMMY_FUNCTION_PASS
#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME)
#endif
+DUMMY_FUNCTION_PASS("tlshoist", TLSVariableHoistPass)
optimisan wrote:
I'll remove this list entirely since it's the same in
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138495
>From 476894ffa1fed64724b91c8b1db9391e09295be6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:47:42 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port InitUndef to NPM
---
llvm/include/llvm/C
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138829
>From dbd76c614cb19179ffc0a20a19341a7e58a1431b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 14:12:36 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port ProcessImplicitDefs to NPM
---
llvm/incl
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138828
>From a9bab6452880f4200f4ce2d8c938eacd68d6bbc7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 11:04:05 +
Subject: [PATCH 1/2] [CodeGen][NPM] Register Function Passes
---
llvm/include/llv
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138491
>From dc9a3165d3625002d2122dfd0e1dbe262a399e74 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 06:30:03 +
Subject: [PATCH] [AMDGPU][NPM] Complete optimized regalloc pipeline
Also fill in s
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138670
>From ea3103a3be32909978894364c1b481cb80c2fc67 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:55:07 +
Subject: [PATCH] [CodeGen][NPM] Read TargetMachine's EnableIPRA option
---
llvm/i
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138670
>From ea3103a3be32909978894364c1b481cb80c2fc67 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:55:07 +
Subject: [PATCH] [CodeGen][NPM] Read TargetMachine's EnableIPRA option
---
llvm/i
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138830
>From 67f7f32e9ca0a8befc28b7504e9e7f141d771eae Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 7 May 2025 08:57:31 +
Subject: [PATCH] [CodeGen][NPM] Account inserted passes for -start/stop
options
-
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138660
>From 838e904009527297d38e79572745a810cfa34d60 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:05:52 +
Subject: [PATCH] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138496
>From ff19035e9f213592109e7ee2c4fb2b667ba9a333 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:58:58 +
Subject: [PATCH] [AMDGPU][NPM] Register AMDGPUWaitSGPRHazards pass
---
llvm/lib/T
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138495
>From 476894ffa1fed64724b91c8b1db9391e09295be6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:47:42 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port InitUndef to NPM
---
llvm/include/llvm/C
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138828
>From a9bab6452880f4200f4ce2d8c938eacd68d6bbc7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 11:04:05 +
Subject: [PATCH 1/2] [CodeGen][NPM] Register Function Passes
---
llvm/include/llv
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138491
>From dc9a3165d3625002d2122dfd0e1dbe262a399e74 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 06:30:03 +
Subject: [PATCH] [AMDGPU][NPM] Complete optimized regalloc pipeline
Also fill in s
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138496
>From ff19035e9f213592109e7ee2c4fb2b667ba9a333 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:58:58 +
Subject: [PATCH] [AMDGPU][NPM] Register AMDGPUWaitSGPRHazards pass
---
llvm/lib/T
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138497
>From 41492e43dad53cefb3ee220a13e75f062351c1cc Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 09:17:40 +
Subject: [PATCH] [CodeGen][NPM] Port PostRAMachineSinking to NPM
---
llvm/include
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138660
>From 838e904009527297d38e79572745a810cfa34d60 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:05:52 +
Subject: [PATCH] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138830
>From 67f7f32e9ca0a8befc28b7504e9e7f141d771eae Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 7 May 2025 08:57:31 +
Subject: [PATCH] [CodeGen][NPM] Account inserted passes for -start/stop
options
-
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/139516
None
Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Aria
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/139517
This replaces the Invalidate pass.
Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSyste
optimisan wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/139516?utm_source=stack-comment-downstack-mergeability-warning
optimisan wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/139517?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/139517
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https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/139517
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/139517
Rate limit · GitHub
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background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
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https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/139517
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/139517
>From ae761dee3ece71d4813b62a2600cf4565b893239 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 12 May 2025 08:02:22 +
Subject: [PATCH 1/2] [CodeGen][NPM] Introduce FreeAllAnalysesPass
This replaces t
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/138828
None
Rate limit · GitHub
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background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
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https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/138830
None
>From da7bc1ef72abe405a4e8819f9b79bc7359213253 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 7 May 2025 08:57:31 +
Subject: [PATCH] [CodeGen][NPM] Account inserted passes for -start/stop
opti
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/138829
None
>From 4c6166ad7ddee5231d9b0ac48e7cf1536ce832f8 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 14:12:36 +
Subject: [PATCH] [CodeGen][NPM] Port ProcessImplicitDefs to NPM
---
llvm/in
optimisan wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/138828?utm_source=stack-comment-downstack-mergeability-warning
optimisan wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/138830?utm_source=stack-comment-downstack-mergeability-warning
@@ -45,3 +45,9 @@ MachineFunctionAnalysis::run(Function &F,
FunctionAnalysisManager &FAM) {
return Result(std::move(MF));
}
+
+PreservedAnalyses FreeAllAnalysesPass::run(Function &F,
+ FunctionAnalysisManager &FAM) {
+ FAM.clear(F,
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/139517
Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Arial,sans
@@ -45,3 +45,9 @@ MachineFunctionAnalysis::run(Function &F,
FunctionAnalysisManager &FAM) {
return Result(std::move(MF));
}
+
+PreservedAnalyses FreeAllAnalysesPass::run(Function &F,
+ FunctionAnalysisManager &FAM) {
+ FAM.clear(F,
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/139517
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@@ -2174,7 +2174,44 @@ void AMDGPUCodeGenPassBuilder::addMachineSSAOptimization(
addPass(SIShrinkInstructionsPass());
}
+void AMDGPUCodeGenPassBuilder::addOptimizedRegAlloc(
+AddMachinePass &addPass) const {
+ if (EnableDCEInRA)
+insertPass(DeadMachineInstructionEli
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138491
>From 3d1996a1d347eb14d6908d789307c0a3eef0568c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 06:30:03 +
Subject: [PATCH] [AMDGPU][NPM] Complete optimized regalloc pipeline
Also fill in s
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138495
>From 7938c63eb0883f47cffd02219400780ede01e559 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:47:42 +
Subject: [PATCH 1/3] [CodeGen][NPM] Port InitUndef to NPM
---
llvm/include/llvm/C
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/139517
>From 67eb18a9d3e49b07491f95dde427f434337612b8 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 12 May 2025 08:02:22 +
Subject: [PATCH 1/4] [CodeGen][NPM] Introduce FreeAllAnalysesPass
This replaces t
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/139517
>From 67eb18a9d3e49b07491f95dde427f434337612b8 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 12 May 2025 08:02:22 +
Subject: [PATCH 1/5] [CodeGen][NPM] Introduce FreeAllAnalysesPass
This replaces t
@@ -382,7 +382,7 @@ FUNCTION_PASS("extra-vector-passes",
FUNCTION_PASS("fix-irreducible", FixIrreduciblePass())
FUNCTION_PASS("flatten-cfg", FlattenCFGPass())
FUNCTION_PASS("float2int", Float2IntPass())
-FUNCTION_PASS("free-all-analyses", FreeAllAnalysesPass())
+FUNCTION_PASS("
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138497
>From aac1ecba7f1c390cd34ec529a20c89b3dfcbaf34 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 09:17:40 +
Subject: [PATCH] [CodeGen][NPM] Port PostRAMachineSinking to NPM
---
llvm/include
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138660
>From 6ecdd40d56c96c02be51a80352a64e6cfa96b748 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:05:52 +
Subject: [PATCH] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138828
>From b9b06240fb34a1019abc3951f38342aaa8955dbe Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 11:04:05 +
Subject: [PATCH 1/2] [CodeGen][NPM] Register Function Passes
---
llvm/include/llv
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138670
>From 9acbf2f2fe9e90a96714e5fb6e0e94f7511c6cbd Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:55:07 +
Subject: [PATCH] [CodeGen][NPM] Read TargetMachine's EnableIPRA option
---
llvm/i
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138829
>From 1c9888a20e8e42d6dadf7da80f90870414b4cdb9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 14:12:36 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port ProcessImplicitDefs to NPM
---
llvm/incl
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138830
>From eb703f4f25a1d8896b7a90c602a6f22888934752 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 7 May 2025 08:57:31 +
Subject: [PATCH] [CodeGen][NPM] Account inserted passes for -start/stop
options
-
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/139516
>From b1efb52e4c7b2c8f2b98947bcc8265237fedb03e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 7 May 2025 09:40:22 +
Subject: [PATCH] [AMDGPU][NPM] Fill in addPreSched2 passes
---
llvm/lib/Target/AM
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138496
>From c644259a62dd20fb84de932f6123882909ba89ed Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:58:58 +
Subject: [PATCH] [AMDGPU][NPM] Register AMDGPUWaitSGPRHazards pass
---
llvm/lib/T
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138496
>From 6ca074427fd58fd75b0404815107f26b5b05f9e1 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:58:58 +
Subject: [PATCH] [AMDGPU][NPM] Register AMDGPUWaitSGPRHazards pass
---
llvm/lib/T
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138828
>From 069082c7d4643b40fb6c986e7bf34c251d6eb99f Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 11:04:05 +
Subject: [PATCH 1/2] [CodeGen][NPM] Register Function Passes
---
llvm/include/llv
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138497
>From f39a6916b0c9fb444a728edc58916fe4cee3fc12 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 09:17:40 +
Subject: [PATCH] [CodeGen][NPM] Port PostRAMachineSinking to NPM
---
llvm/include
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138670
>From 7dcc3168ef19af5e5a0325332e298b9a9b2ee3e0 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:55:07 +
Subject: [PATCH] [CodeGen][NPM] Read TargetMachine's EnableIPRA option
---
llvm/i
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138496
>From 961d9a4d20687f1b7ab8761982f33531e0ee173c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:58:58 +
Subject: [PATCH] [AMDGPU][NPM] Register AMDGPUWaitSGPRHazards pass
---
llvm/lib/T
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138660
>From 6d6546da6f88c149757ae9e60351e1a2dec7126a Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 09:05:52 +
Subject: [PATCH] [CodeGen][NPM] VirtRegRewriter: Set VirtReg flag
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/139517
>From f290be1035fa428df66b5c2be316178de269ffa6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 12 May 2025 08:02:22 +
Subject: [PATCH 1/5] [CodeGen][NPM] Introduce FreeAllAnalysesPass
This replaces t
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/139516
>From a4d05859096953bb45844ba11ba3e7c989334d10 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 7 May 2025 09:40:22 +
Subject: [PATCH] [AMDGPU][NPM] Fill in addPreSched2 passes
---
llvm/lib/Target/AM
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138830
>From b0f06a702546b3ed7d89bfa3256cbeea784f2b82 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 7 May 2025 08:57:31 +
Subject: [PATCH] [CodeGen][NPM] Account inserted passes for -start/stop
options
-
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138829
>From 35252487f30d1f6e6045cb4ab30ddae2cceaaa90 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 6 May 2025 14:12:36 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port ProcessImplicitDefs to NPM
---
llvm/incl
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/148108
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