[llvm-branch-commits] [llvm] [AMDGPU] Early bail in getFunctionCodeSize for meta inst. NFC. (PR #127129)

2025-02-13 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/127129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (PR #126763)

2025-02-12 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/126763 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940 ISA doc (PR #126906)

2025-02-12 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/126906 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Remove FeatureForceStoreSC0SC1 (PR #126878)

2025-02-12 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/126878 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Switch to MF.estimateFunctionSizeInBytes() (PR #127246)

2025-02-14 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/127246?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU] Switch to MF.estimateFunctionSizeInBytes() (PR #127246)

2025-02-14 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/127246 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Switch to MF.estimateFunctionSizeInBytes() (PR #127246)

2025-02-14 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/127246 Both methods are equally inaccurate, we need to switch to MCExpr for better results in the future. >From 99b5a597f7a888269ebdbd0f054d6511b2c9950b Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Fri,

[llvm-branch-commits] [llvm] [AMDGPU] Early bail in getFunctionCodeSize for meta inst. NFC. (PR #127129)

2025-02-14 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > There is also MF.estimateFunctionSizeInBytes(), probably should use that as a > stop gap until MC computes this https://github.com/llvm/llvm-project/pull/127246 For some reason it is not const and also can overestimate code size. https://github.com/llvm/llvm-project/pull/127

[llvm-branch-commits] [llvm] [AMDGPU] Respect MBB alignment in the getFunctionCodeSize() (PR #127142)

2025-02-14 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/127142 >From 63e9a995b61b17c2fe064ca4142c58e541688cf4 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Thu, 13 Feb 2025 14:46:37 -0800 Subject: [PATCH] [AMDGPU] Respect MBB alignment in the getFunctionCodeSi

[llvm-branch-commits] [llvm] [AMDGPU] Respect MBB alignment in the getFunctionCodeSize() (PR #127142)

2025-02-14 Thread Stanislav Mekhanoshin via llvm-branch-commits
@@ -212,6 +212,8 @@ uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF) { uint64_t CodeSize = 0; for (const MachineBasicBlock &MBB : MF) { +CodeSize = alignTo(CodeSize, MBB.getAlignment()); rampitec wrote: Thanks. Added comment. h

[llvm-branch-commits] [llvm] AMDGPU: Disable most fmed3 folds for strictfp (PR #139530)

2025-05-12 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/139530 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Use minnum instead of maxnum for fmed3 src2-nan fold (PR #139531)

2025-05-12 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/139531 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle minimumnum/maximumnum in fneg combines (PR #139133)

2025-05-08 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. LGTM, although I do not see practical improvements in the tests. https://github.com/llvm/llvm-project/pull/139133 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://li

[llvm-branch-commits] [llvm] AMDGPU: Add baseline tests for min3/max3 from minimumnum/maximumnum (PR #139136)

2025-05-08 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/139136 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Form min3/max3 from minimumnum/maximumnum (PR #139137)

2025-05-08 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/139137 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Test more subtargets in minimumnum/maximumnum tests (PR #139144)

2025-05-08 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/139144 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add minimumnum/maximumnum tests with amdgpu-ieee=0 (PR #139145)

2025-05-08 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/139145 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Check for subreg match when folding through reg_sequence (PR #140582)

2025-05-19 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/140582 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add overflow operations to isBoolSGPR (PR #141803)

2025-05-28 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/141803 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Automate creation of byte_sel dags. NFCI. (PR #140155)

2025-05-15 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/140155 None >From 071898b2e2b1f23e67ad5471df2088a0db167555 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Thu, 15 May 2025 15:41:55 -0700 Subject: [PATCH] [AMDGPU] Automate creation of byte_sel dags. NFCI

[llvm-branch-commits] [llvm] [AMDGPU] Automate creation of byte_sel dags. NFCI. (PR #140155)

2025-05-15 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/140155 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Automate creation of byte_sel dags. NFCI. (PR #140155)

2025-05-15 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/140155?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] AMDGPU: Form v_med_f32 from minimumnum/maximumnum immediate pattern (PR #141048)

2025-05-22 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/141048 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle other fmin flavors in fract combine (PR #141987)

2025-05-29 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/141987 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Report special input intrinsics as free (PR #141948)

2025-05-29 Thread Stanislav Mekhanoshin via llvm-branch-commits
@@ -704,8 +704,29 @@ static bool intrinsicHasPackedVectorBenefit(Intrinsic::ID ID) { InstructionCost GCNTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const { - if (ICA.getID() == Intrinsic::f

[llvm-branch-commits] [llvm] AMDGPU: Report special input intrinsics as free (PR #141948)

2025-05-29 Thread Stanislav Mekhanoshin via llvm-branch-commits
@@ -704,8 +704,29 @@ static bool intrinsicHasPackedVectorBenefit(Intrinsic::ID ID) { InstructionCost GCNTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const { - if (ICA.getID() == Intrinsic::f

[llvm-branch-commits] [llvm] AMDGPU: Add baseline cost model tests for special argument intrinsics (PR #141947)

2025-05-29 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/141947 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Report special input intrinsics as free (PR #141948)

2025-05-29 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/141948 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC. (PR #142910)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/142910 None >From 321eb42ae21d0d3156fb5ef15f5b336551a20c5b Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 4 Jun 2025 23:46:28 -0700 Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC. -

[llvm-branch-commits] [llvm] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs) (PR #142911)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/142911 None >From 44a9017e98eff94456889a528a166d6aabca842d Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 4 Jun 2025 23:49:43 -0700 Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs) --

[llvm-branch-commits] [llvm] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs) (PR #142911)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142911?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC. (PR #142910)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142910?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC. (PR #142910)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/142910 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs) (PR #142911)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/142911 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (PR #145024)

2025-06-20 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec commented: Do you assume that at this stage there are no accvgpr_write/read instructions, but only COPY? https://github.com/llvm/llvm-project/pull/145024 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.o

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/145152 None >From ae162ef51dd115f68c86cce893a0ae7baf99e6b9 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Fri, 20 Jun 2025 12:24:47 -0700 Subject: [PATCH] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145152?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: Actually the first codegen test for the subtarget. https://github.com/llvm/llvm-project/pull/145152 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-comm

[llvm-branch-commits] [llvm] [AMDGPU] Autogenerate dst bytesel asm. NFCI. (PR #143429)

2025-06-09 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/143429?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU] Autogenerate dst bytesel asm. NFCI. (PR #143429)

2025-06-09 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/143429 Needed for future t16 support. >From 3c462dc48271923cf466e0e0c2c86f26bb69eb11 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Mon, 9 Jun 2025 11:53:11 -0700 Subject: [PATCH] [AMDGPU] Autogenerate ds

[llvm-branch-commits] [llvm] [AMDGPU] Autogenerate bitop3 asm and dags. NFCI. (PR #143430)

2025-06-09 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/143430 None >From 1d58dc465ebd0049e9f4d6b9c32b65b72b88be3e Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Mon, 9 Jun 2025 12:47:55 -0700 Subject: [PATCH] [AMDGPU] Autogenerate bitop3 asm and dags. NFCI.

[llvm-branch-commits] [llvm] [AMDGPU] Autogenerate dst bytesel asm. NFCI. (PR #143429)

2025-06-09 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/143429 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Autogenerate bitop3 asm and dags. NFCI. (PR #143430)

2025-06-09 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/143430?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU] Autogenerate bitop3 asm and dags. NFCI. (PR #143430)

2025-06-09 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/143430 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits
@@ -9669,6 +9670,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const { int MCOp = AMDGPU::getMCOpcode(Opcode, Gen); + if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts()) rampitec wrote: 0x means it is already a real opcode. 0x means it is n

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits
@@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx1250 -show-mc-encoding -verify-machineinstrs < %s | FileCheck -check-prefix=GFX1250 %s rampitec wrote: Will do. This is a very old

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/145152 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Make <2 x bfloat> fneg legal (PR #142870)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/142870 None >From 27a5d3f0d06f1fc9efe6ed482c5ace394faff88e Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 4 Jun 2025 15:37:20 -0700 Subject: [PATCH] [AMDGPU] Make <2 x bfloat> fneg legal --- llvm/l

[llvm-branch-commits] [llvm] [AMDGPU] Make <2 x bfloat> fneg legal (PR #142870)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142870?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU] Make <2 x bfloat> fneg legal (PR #142870)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/142870 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Make <2 x bfloat> fneg legal (PR #142870)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
@@ -1835,6 +1835,11 @@ def : GCNPat < (S_XOR_B32 SReg_32:$src, (S_MOV_B32 (i32 0x80008000))) >; +def : GCNPat < rampitec wrote: I can. But fabs needs the same, so for now it will be isolated. https://github.com/llvm/llvm-project/pull/142870 ___

[llvm-branch-commits] [llvm] [AMDGPU] Make <2 x bfloat> fneg legal (PR #142870)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/142870 >From 80608a949bf530cf77faa7dac7dd1a2f9aa357c1 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 4 Jun 2025 15:37:20 -0700 Subject: [PATCH] [AMDGPU] Make <2 x bfloat> fneg legal --- llvm/lib/Tar

[llvm-branch-commits] [llvm] [AMDGPU] Make <2 x bfloat> fneg legal (PR #142870)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/142870 >From 80608a949bf530cf77faa7dac7dd1a2f9aa357c1 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 4 Jun 2025 15:37:20 -0700 Subject: [PATCH] [AMDGPU] Make <2 x bfloat> fneg legal --- llvm/lib/Tar

[llvm-branch-commits] [llvm] [AMDGPU] Make <2 x bfloat> fneg legal (PR #142870)

2025-06-04 Thread Stanislav Mekhanoshin via llvm-branch-commits
@@ -1835,6 +1835,11 @@ def : GCNPat < (S_XOR_B32 SReg_32:$src, (S_MOV_B32 (i32 0x80008000))) >; +def : GCNPat < rampitec wrote: Done https://github.com/llvm/llvm-project/pull/142870 ___ llvm-branch-commits mailin

[llvm-branch-commits] [llvm] AMDGPU: Handle vectors in copysign magnitude sign case (PR #142156)

2025-05-30 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/142156 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Handle vectors in copysign sign type combine (PR #142157)

2025-05-30 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/142157 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Improve v4f16/v4bf16 copysign handling (PR #142174)

2025-05-30 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/142174 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Improve v8f16/v8bf16 copysign handling (PR #142175)

2025-05-30 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/142175 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Improve v32f16/v32bf16 copysign handling (PR #142177)

2025-05-30 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/142177 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Make v2f16/v2bf16 copysign legal (PR #142173)

2025-05-30 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. LGTM with a nit: title says it is legal, but it is custom. https://github.com/llvm/llvm-project/pull/142173 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.ll

[llvm-branch-commits] [llvm] AMDGPU: Move bf16 copysign tests to separate file (PR #142114)

2025-05-30 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/142114 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Improve v16f16/v16bf16 copysign handling (PR #142176)

2025-05-30 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/142176 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add more f16 copysign tests (PR #142115)

2025-05-30 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/142115 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs) (PR #142911)

2025-06-05 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/142911 >From c8524591999f495dd86261daecc44071737a227b Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 4 Jun 2025 23:49:43 -0700 Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs) --- llv

[llvm-branch-commits] [llvm] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC. (PR #142910)

2025-06-05 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/142910 >From 641fb5022daeca9b71527e18ea2df7982856a105 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 4 Jun 2025 23:46:28 -0700 Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC. --- ll

[llvm-branch-commits] [llvm] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC. (PR #142910)

2025-06-05 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/142910 >From 641fb5022daeca9b71527e18ea2df7982856a105 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 4 Jun 2025 23:46:28 -0700 Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC. --- ll

[llvm-branch-commits] [llvm] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs) (PR #142911)

2025-06-05 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/142911 >From c8524591999f495dd86261daecc44071737a227b Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 4 Jun 2025 23:49:43 -0700 Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs) --- llv

[llvm-branch-commits] [llvm] [AMDGPU] gfx1250 VOPD MC tests. NFC. (PR #147826)

2025-07-09 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/147826?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU] gfx1250 VOPD MC tests. NFC. (PR #147826)

2025-07-09 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/147826 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] gfx1250 VOPD MC overflow tests. NFC. (PR #147826)

2025-07-09 Thread Stanislav Mekhanoshin via llvm-branch-commits
@@ -9937,3 +9937,6339 @@ v_dual_mul_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 // GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xcc,0xc8,0xff

[llvm-branch-commits] [llvm] [AMDGPU] gfx1250 VOPD MC overflow tests. NFC. (PR #147826)

2025-07-09 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > Not sure what's "overflow" about these Joe asked to split the test because github does not show long files in the web interface. I have just cut it around ~1 lines so it is shown for review. https://github.com/llvm/llvm-project/pull/147826

[llvm-branch-commits] [llvm] [AMDGPU] Autogenerate gfx1250 vopd tests. NFC. (PR #147918)

2025-07-10 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/147918?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU] Autogenerate gfx1250 vopd tests. NFC. (PR #147918)

2025-07-10 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/147918 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] gfx1250 VOPD MC overflow tests. NFC. (PR #147826)

2025-07-10 Thread Stanislav Mekhanoshin via llvm-branch-commits
@@ -9937,3 +9937,6339 @@ v_dual_mul_f32 v255, -1, v4 :: v_dual_subrev_f32 v6, src_scc, v5 v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 // GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4 ; encoding: [0x7c,0x0a,0xcc,0xc8,0xff

[llvm-branch-commits] [llvm] [AMDGPU] Autogenerate gfx1250 vopd tests. NFC. (PR #147918)

2025-07-10 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: I know github does not help. This is the example change: ``` v_dual_add_f32 v255, s105, v2 :: v_dual_add_f32 v7, s1, v3 // GFX1250: v_dual_add_f32 v255, s105, v2 :: v_dual_add_f32 v7, s1, v3 ; encoding: [0x69,0x40,0x10,0xcf,0x01,0x00,0x02,0x00,0xff,0x03,0x00,0x07] -// W64-ERR:

[llvm-branch-commits] [llvm] [AMDGPU] Negative gfx1250 v_dual_cndmask_b32 tests. NFC. (PR #148057)

2025-07-10 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148057?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU] Negative gfx1250 v_dual_cndmask_b32 tests. NFC. (PR #148057)

2025-07-10 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/148057 None >From 10f072f90c8c575c670a7ad50c8f8531144a27d3 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Thu, 10 Jul 2025 13:47:02 -0700 Subject: [PATCH] [AMDGPU] Negative gfx1250 v_dual_cndmask_b32 test

[llvm-branch-commits] [llvm] [AMDGPU] Negative gfx1250 v_dual_cndmask_b32 tests. NFC. (PR #148057)

2025-07-10 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/148057 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_pk_f16_bf8` on gfx1250 (PR #145753)

2025-06-25 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/145753 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_pk_f16_fp8` on gfx1250 (PR #145747)

2025-06-25 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/145747 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Use 64-bit literals in codegen on gfx1250 (PR #148727)

2025-07-14 Thread Stanislav Mekhanoshin via llvm-branch-commits
@@ -447,14 +447,42 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { return; } + bool IsGCN = CurDAG->getSubtarget().getTargetTriple().isAMDGCN(); + if (IsGCN && Subtarget->has64BitLiterals() && VT.getSizeInBits() == 64 && + CurDAG->

[llvm-branch-commits] [llvm] [AMDGPU] Add support for `v_sqrt_bf16` on gfx1250 (PR #148921)

2025-07-15 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/148921 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Select flat GVS loads on gfx1250 (PR #149183)

2025-07-16 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/149183?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU] Select flat GVS loads on gfx1250 (PR #149183)

2025-07-16 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/149183 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Select flat GVS loads on gfx1250 (PR #149183)

2025-07-16 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: It will create some downstream conflicts, not all flat features are upstreamed yet. In particular some of the patterns shall take CPol operand, but that is a later patch. https://github.com/llvm/llvm-project/pull/149183 ___ llvm-branc

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_sin_bf16` on gfx1250 (PR #149241)

2025-07-17 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/149241 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add pass to replace constant materialize with AV pseudos (PR #149292)

2025-07-17 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/149292 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Fix introducing use of killed vgpr in gfx908 agpr copy (PR #149291)

2025-07-17 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/149291 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_sat_pk4_i4_[i8, u8]` on gfx1250 (PR #149528)

2025-07-18 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/149528 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [MI400][SDAG] Lower unsafe bf16 divisions (PR #149628)

2025-07-21 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/149628 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Mark `amdgcn_tanh` as canonicalized (PR #150059)

2025-07-22 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/150059 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] gfx1250 vmem prefetch target intrinsics and builtins (PR #150466)

2025-07-24 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/150466?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [clang] [llvm] [AMDGPU] gfx1250 vmem prefetch target intrinsics and builtins (PR #150466)

2025-07-24 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/150466 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] gfx1250 vmem prefetch target intrinsics and builtins (PR #150466)

2025-07-24 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/150466 None >From c140539efa4d71c53853b16a38f88c9dae2b2718 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Thu, 24 Jul 2025 10:06:26 -0700 Subject: [PATCH] [AMDGPU] gfx1250 vmem prefetch target intrinsics

[llvm-branch-commits] [clang] [llvm] [AMDGPU] gfx1250 vmem prefetch target intrinsics and builtins (PR #150466)

2025-07-24 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec updated https://github.com/llvm/llvm-project/pull/150466 >From d245f4b7dad916b1cfc54424bbd5aa94f3bb1173 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Thu, 24 Jul 2025 10:06:26 -0700 Subject: [PATCH] [AMDGPU] gfx1250 vmem prefetch target intrinsics and bu

[llvm-branch-commits] [llvm] [AMDGPU] Select VMEM prefetch for llvm.prefetch on gfx1250 (PR #150493)

2025-07-24 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/150493 We have a choice to use a scalar or vector prefetch for an uniform pointer. Since we do not have scalar stores our scalar cache is practically readonly. The rw argument of the prefetch intrinsic is used to force

[llvm-branch-commits] [llvm] [AMDGPU] Select VMEM prefetch for llvm.prefetch on gfx1250 (PR #150493)

2025-07-24 Thread Stanislav Mekhanoshin via llvm-branch-commits
https://github.com/rampitec ready_for_review https://github.com/llvm/llvm-project/pull/150493 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Select VMEM prefetch for llvm.prefetch on gfx1250 (PR #150493)

2025-07-24 Thread Stanislav Mekhanoshin via llvm-branch-commits
rampitec wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/150493?utm_source=stack-comment-downstack-mergeability-warning"

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