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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/127246?utm_source=stack-comment-downstack-mergeability-warning"
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Both methods are equally inaccurate, we need to switch to MCExpr
for better results in the future.
>From 99b5a597f7a888269ebdbd0f054d6511b2c9950b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Fri,
rampitec wrote:
> There is also MF.estimateFunctionSizeInBytes(), probably should use that as a
> stop gap until MC computes this
https://github.com/llvm/llvm-project/pull/127246
For some reason it is not const and also can overestimate code size.
https://github.com/llvm/llvm-project/pull/127
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/127142
>From 63e9a995b61b17c2fe064ca4142c58e541688cf4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 13 Feb 2025 14:46:37 -0800
Subject: [PATCH] [AMDGPU] Respect MBB alignment in the getFunctionCodeSi
@@ -212,6 +212,8 @@ uint64_t SIProgramInfo::getFunctionCodeSize(const
MachineFunction &MF) {
uint64_t CodeSize = 0;
for (const MachineBasicBlock &MBB : MF) {
+CodeSize = alignTo(CodeSize, MBB.getAlignment());
rampitec wrote:
Thanks. Added comment.
h
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LGTM, although I do not see practical improvements in the tests.
https://github.com/llvm/llvm-project/pull/139133
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LGTM
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LGTM
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None
>From 071898b2e2b1f23e67ad5471df2088a0db167555 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 15 May 2025 15:41:55 -0700
Subject: [PATCH] [AMDGPU] Automate creation of byte_sel dags. NFCI
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> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/140155?utm_source=stack-comment-downstack-mergeability-warning"
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@@ -704,8 +704,29 @@ static bool intrinsicHasPackedVectorBenefit(Intrinsic::ID
ID) {
InstructionCost
GCNTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind) const {
- if (ICA.getID() == Intrinsic::f
@@ -704,8 +704,29 @@ static bool intrinsicHasPackedVectorBenefit(Intrinsic::ID
ID) {
InstructionCost
GCNTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind) const {
- if (ICA.getID() == Intrinsic::f
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None
>From 321eb42ae21d0d3156fb5ef15f5b336551a20c5b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:46:28 -0700
Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC.
-
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/142911
None
>From 44a9017e98eff94456889a528a166d6aabca842d Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:49:43 -0700
Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs)
--
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142911?utm_source=stack-comment-downstack-mergeability-warning"
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142910?utm_source=stack-comment-downstack-mergeability-warning"
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https://github.com/rampitec commented:
Do you assume that at this stage there are no accvgpr_write/read instructions,
but only COPY?
https://github.com/llvm/llvm-project/pull/145024
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https://github.com/llvm/llvm-project/pull/145152
None
>From ae162ef51dd115f68c86cce893a0ae7baf99e6b9 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Fri, 20 Jun 2025 12:24:47 -0700
Subject: [PATCH] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145152?utm_source=stack-comment-downstack-mergeability-warning"
rampitec wrote:
Actually the first codegen test for the subtarget.
https://github.com/llvm/llvm-project/pull/145152
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> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/143429?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/143429
Needed for future t16 support.
>From 3c462dc48271923cf466e0e0c2c86f26bb69eb11 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 9 Jun 2025 11:53:11 -0700
Subject: [PATCH] [AMDGPU] Autogenerate ds
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/143430
None
>From 1d58dc465ebd0049e9f4d6b9c32b65b72b88be3e Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 9 Jun 2025 12:47:55 -0700
Subject: [PATCH] [AMDGPU] Autogenerate bitop3 asm and dags. NFCI.
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/143429
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/143430?utm_source=stack-comment-downstack-mergeability-warning"
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@@ -9669,6 +9670,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
+ if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts())
rampitec wrote:
0x means it is already a real opcode. 0x means it is n
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx1250 -show-mc-encoding -verify-machineinstrs
< %s | FileCheck -check-prefix=GFX1250 %s
rampitec wrote:
Will do. This is a very old
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None
>From 27a5d3f0d06f1fc9efe6ed482c5ace394faff88e Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 15:37:20 -0700
Subject: [PATCH] [AMDGPU] Make <2 x bfloat> fneg legal
---
llvm/l
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142870?utm_source=stack-comment-downstack-mergeability-warning"
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@@ -1835,6 +1835,11 @@ def : GCNPat <
(S_XOR_B32 SReg_32:$src, (S_MOV_B32 (i32 0x80008000)))
>;
+def : GCNPat <
rampitec wrote:
I can. But fabs needs the same, so for now it will be isolated.
https://github.com/llvm/llvm-project/pull/142870
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142870
>From 80608a949bf530cf77faa7dac7dd1a2f9aa357c1 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 15:37:20 -0700
Subject: [PATCH] [AMDGPU] Make <2 x bfloat> fneg legal
---
llvm/lib/Tar
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142870
>From 80608a949bf530cf77faa7dac7dd1a2f9aa357c1 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 15:37:20 -0700
Subject: [PATCH] [AMDGPU] Make <2 x bfloat> fneg legal
---
llvm/lib/Tar
@@ -1835,6 +1835,11 @@ def : GCNPat <
(S_XOR_B32 SReg_32:$src, (S_MOV_B32 (i32 0x80008000)))
>;
+def : GCNPat <
rampitec wrote:
Done
https://github.com/llvm/llvm-project/pull/142870
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LGTM with a nit: title says it is legal, but it is custom.
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142911
>From c8524591999f495dd86261daecc44071737a227b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:49:43 -0700
Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs)
---
llv
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142910
>From 641fb5022daeca9b71527e18ea2df7982856a105 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:46:28 -0700
Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC.
---
ll
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142910
>From 641fb5022daeca9b71527e18ea2df7982856a105 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:46:28 -0700
Subject: [PATCH] [AMDGPU] Baseline fneg-fabs.bf16.ll tests. NFC.
---
ll
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/142911
>From c8524591999f495dd86261daecc44071737a227b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Jun 2025 23:49:43 -0700
Subject: [PATCH] [AMDGPU] Patterns for <2 x bfloat> fneg (fabs)
---
llv
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/147826?utm_source=stack-comment-downstack-mergeability-warning"
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@@ -9937,3 +9937,6339 @@ v_dual_mul_f32 v255, -1, v4 :: v_dual_subrev_f32 v6,
src_scc, v5
v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
// GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456,
v4 ; encoding: [0x7c,0x0a,0xcc,0xc8,0xff
rampitec wrote:
> Not sure what's "overflow" about these
Joe asked to split the test because github does not show long files in the web
interface. I have just cut it around ~1 lines so it is shown for review.
https://github.com/llvm/llvm-project/pull/147826
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/147918?utm_source=stack-comment-downstack-mergeability-warning"
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@@ -9937,3 +9937,6339 @@ v_dual_mul_f32 v255, -1, v4 :: v_dual_subrev_f32 v6,
src_scc, v5
v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456, v4
// GFX12: v_dual_mul_f32 v6, null, v5 :: v_dual_subrev_f32 v255, 0xaf123456,
v4 ; encoding: [0x7c,0x0a,0xcc,0xc8,0xff
rampitec wrote:
I know github does not help. This is the example change:
```
v_dual_add_f32 v255, s105, v2 :: v_dual_add_f32 v7, s1, v3
// GFX1250: v_dual_add_f32 v255, s105, v2 :: v_dual_add_f32 v7, s1, v3 ;
encoding: [0x69,0x40,0x10,0xcf,0x01,0x00,0x02,0x00,0xff,0x03,0x00,0x07]
-// W64-ERR:
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148057?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/148057
None
>From 10f072f90c8c575c670a7ad50c8f8531144a27d3 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 10 Jul 2025 13:47:02 -0700
Subject: [PATCH] [AMDGPU] Negative gfx1250 v_dual_cndmask_b32 test
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https://github.com/llvm/llvm-project/pull/148057
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@@ -447,14 +447,42 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N,
unsigned RegClassID) {
return;
}
+ bool IsGCN = CurDAG->getSubtarget().getTargetTriple().isAMDGCN();
+ if (IsGCN && Subtarget->has64BitLiterals() && VT.getSizeInBits() == 64 &&
+ CurDAG->
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/148921
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/149183?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/149183
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rampitec wrote:
It will create some downstream conflicts, not all flat features are upstreamed
yet. In particular some of the patterns shall take CPol operand, but that is a
later patch.
https://github.com/llvm/llvm-project/pull/149183
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https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/149241
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https://github.com/rampitec approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/149292
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https://github.com/llvm/llvm-project/pull/149528
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https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/150059
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/150466?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/150466
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https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/150466
None
>From c140539efa4d71c53853b16a38f88c9dae2b2718 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 24 Jul 2025 10:06:26 -0700
Subject: [PATCH] [AMDGPU] gfx1250 vmem prefetch target intrinsics
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/150466
>From d245f4b7dad916b1cfc54424bbd5aa94f3bb1173 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 24 Jul 2025 10:06:26 -0700
Subject: [PATCH] [AMDGPU] gfx1250 vmem prefetch target intrinsics and bu
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/150493
We have a choice to use a scalar or vector prefetch for an uniform
pointer. Since we do not have scalar stores our scalar cache is
practically readonly. The rw argument of the prefetch intrinsic is
used to force
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/150493
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/150493?utm_source=stack-comment-downstack-mergeability-warning"
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