@@ -698,6 +698,16 @@ class SIInsertWaitcnts {
// Return the appropriate VMEM_*_ACCESS type for Inst, which must be a VMEM
or
// FLAT instruction.
WaitEventType getVmemWaitEventType(const MachineInstr &Inst) const {
+switch (Inst.getOpcode()) {
Pierre
https://github.com/Pierre-vh converted_to_draft
https://github.com/llvm/llvm-project/pull/135340
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@@ -19,7 +19,7 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: renamable $vgpr0 = GLOBAL_LOAD_DWORD_SADDR renamable
$sgpr2_sgpr3, killed $vgpr0, 0, 0, implicit $exec :: (load (s32), addrspace 1)
; GFX12-NEXT: GLOBAL_INV 16, implicit $exec
-; GFX12-NEXT: S_WAIT_L
Pierre-vh wrote:
### Merge activity
* **Apr 22, 8:43 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/135340).
https://github.com/llvm/llvm-project/pull/135340
__
Pierre-vh wrote:
> Patch looks OK to me, unless you are still worried about the global_inv
> loadcnt decrement ordering thing.
It's a bit concerning but in any case it's not the fault of this patch, so I'll
land and track that separately. Same for the optimization
https://github.com/llvm/llvm
@@ -698,6 +698,16 @@ class SIInsertWaitcnts {
// Return the appropriate VMEM_*_ACCESS type for Inst, which must be a VMEM
or
// FLAT instruction.
WaitEventType getVmemWaitEventType(const MachineInstr &Inst) const {
+switch (Inst.getOpcode()) {
Pierre
@@ -19,7 +19,7 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: renamable $vgpr0 = GLOBAL_LOAD_DWORD_SADDR renamable
$sgpr2_sgpr3, killed $vgpr0, 0, 0, implicit $exec :: (load (s32), addrspace 1)
; GFX12-NEXT: GLOBAL_INV 16, implicit $exec
-; GFX12-NEXT: S_WAIT_L
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Pierre-vh wrote:
### Merge activity
* **Apr 14, 4:03 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/131624).
https://github.com/llvm/llvm-project/pull/131624
__
Pierre-vh wrote:
> Just a quick side question, do we have any write-up or documentation about
> the memory model?
AMDGPUUsage has a memory model section for each arch
https://github.com/llvm/llvm-project/pull/135340
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https://github.com/Pierre-vh commented:
Can you add a testcase in each file with MI flags on the instruction?
You have code that preserve flags which needs to be tested
https://github.com/llvm/llvm-project/pull/132382
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@@ -237,6 +237,21 @@ void RegBankLegalizeHelper::lowerS_BFE(MachineInstr &MI) {
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst) == V4S16 ? V2S16 : S32;
-
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@@ -131,6 +131,40 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI,
LLT WideTy,
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ Register Src = MI
@@ -485,7 +504,8 @@ LLT
RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) {
case UniInVgprB64:
if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(0, 64) ||
-Ty == LLT:
@@ -286,6 +287,22 @@ void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr
&MI) {
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerSplitTo32Sel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst) == V4S16 ? V2S16 : S32;
-
@@ -131,6 +131,40 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI,
LLT WideTy,
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ Register Src = MI
@@ -198,7 +198,8 @@ UniformityLLTOpPredicateID LLTToBId(LLT Ty) {
return B32;
if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(1, 64) ||
- Ty == LLT::pointer(4, 64))
+ Ty == LLT::pointer(4,
https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/131063
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https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/131062
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https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/129059
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131624
>From d85d13bb1824c716d19179a1fbeca48f4ed37368 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:54:59 +0100
Subject: [PATCH 1/3] [GlobalISel] Combine redundant sext_inreg
---
.../llvm/CodeGe
Pierre-vh wrote:
> Then isUnneededShiftMask should probably recognize more forms of the pattern
Yes, but with a cast operation it gets tricky. If I add `(zext node:$src0)` to
the PatFrag, it doesn't work because the PatFrag is always used like this:
`(cshl_32 (i32 $src0))`. As `$src0` is infer
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131624
>From f4c801437460aef9b9c2e5f49d1e98ec90fadb16 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:54:59 +0100
Subject: [PATCH 1/3] [GlobalISel] Combine redundant sext_inreg
---
.../llvm/CodeGe
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131624
>From f4c801437460aef9b9c2e5f49d1e98ec90fadb16 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:54:59 +0100
Subject: [PATCH 1/3] [GlobalISel] Combine redundant sext_inreg
---
.../llvm/CodeGe
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From ed5f76fd041f3d343168aca5266cf991a0d56bce Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From ed5f76fd041f3d343168aca5266cf991a0d56bce Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/141589?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/141589
None
>From e5f24775ff988e5c6ac302f36b010fc0421eca34 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/
https://github.com/Pierre-vh edited
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Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/141590?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh ready_for_review
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Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/141591?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh edited
https://github.com/llvm/llvm-project/pull/141591
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 687bf11493d38ba323e90c1b40ae6919d48ed016 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH] [AMDGPU] Add KnownBits simplification combines to
RegBankCombiner
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 150fe8c86c080a075fef344b20cd15b1097d3f29 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/lib/Ta
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 687bf11493d38ba323e90c1b40ae6919d48ed016 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH] [AMDGPU] Add KnownBits simplification combines to
RegBankCombiner
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 150fe8c86c080a075fef344b20cd15b1097d3f29 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/lib/Ta
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From c7a0fb8f9846faa98cd5dbf3d71d5149051fa8a8 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 7c8f90225928c0dbffcfa03bd20da3419a80095f Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 7c8f90225928c0dbffcfa03bd20da3419a80095f Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 9e7f29551b788d9060aec2168920554df41ff5df Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 9e7f29551b788d9060aec2168920554df41ff5df Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From c7a0fb8f9846faa98cd5dbf3d71d5149051fa8a8 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From efa6a12fedf3c87678a1df1e5d03ff1e58531625 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/141591
None
>From d102621b16b8c893c4b56248d9c4cf59b3e1bf6e Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH] [AMDGPU] Add KnownBits simplification combines to
RegBankCom
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/141589
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From efa6a12fedf3c87678a1df1e5d03ff1e58531625 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/lib/Ta
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 62031c0316c73a3650223721347854fd0c45e730 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH] [AMDGPU] Add KnownBits simplification combines to
RegBankCombiner
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From efa6a12fedf3c87678a1df1e5d03ff1e58531625 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/lib/Ta
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 62031c0316c73a3650223721347854fd0c45e730 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH] [AMDGPU] Add KnownBits simplification combines to
RegBankCombiner
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From e253bde72750576cab699ad1b6b872fbf60dffe9 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From b249611564844064031ca7be93aeda517fad37ea Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From e253bde72750576cab699ad1b6b872fbf60dffe9 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From b249611564844064031ca7be93aeda517fad37ea Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh ready_for_review
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Pierre-vh wrote:
### Merge activity
* **May 16, 4:09 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/140208).
https://github.com/llvm/llvm-project/pull/140208
__
Pierre-vh wrote:
### Merge activity
* **May 16, 4:09 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/140207).
https://github.com/llvm/llvm-project/pull/140207
__
@@ -742,6 +744,23 @@ GCNTTIImpl::getIntrinsicInstrCost(const
IntrinsicCostAttributes &ICA,
break;
case Intrinsic::copysign:
return NElts * getFullRateInstrCost();
+ case Intrinsic::minimumnum:
+ case Intrinsic::maximumnum: {
+// Instruction + 2 canonicalizes. F
@@ -281,6 +281,13 @@ class GCNTTIImpl final : public
BasicTTIImplBase {
void collectKernelLaunchBounds(
const Function &F,
SmallVectorImpl> &LB) const override;
+
+ enum class KnownIEEEMode { Unknown, On, Off };
+
+ /// Return KnownIEEEMode::On if we know if th
https://github.com/Pierre-vh approved this pull request.
unrelated to this patch but `KnownIEEEMode::Unknown` looks weird, maybe it
should just be named `IEEEMode`?
https://github.com/llvm/llvm-project/pull/141945
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https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/141904
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https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/141946
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https://github.com/Pierre-vh edited
https://github.com/llvm/llvm-project/pull/141945
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@@ -741,8 +743,8 @@ GCNTTIImpl::getIntrinsicInstrCost(const
IntrinsicCostAttributes &ICA,
case Intrinsic::copysign:
return NElts * getFullRateInstrCost();
case Intrinsic::canonicalize: {
-assert(SLT != MVT::f64);
-InstRate = getFullRateInstrCost();
+InstRat
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142602?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142601?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142603?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/142603
Test P0 through P6 + P8 for both S/VGPRs.
>From 6748dc972c09a7070118ce0aefa9677b3d7aa488 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 15:03:01 +0200
Subject: [PATCH] [AMDGPU] Improve test cov
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/142604
None
>From f9141055a09fc376354f901932b0a39e28d58c35 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 15:08:06 +0200
Subject: [PATCH] [AMDGPU] New RegBankSelect: Add rules for `G_PTRTOINT` and
`G
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/142601
None
>From 5805695f988eac8818a520f8e84f3d50ad79a12a Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 13:27:55 +0200
Subject: [PATCH] [AMDGPU] New RegBanKSelect: Add S128 types
---
llvm/lib/Targ
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/142600
None
>From 2665b0c4b8b885630f2dbd4f8e523d7eecc64897 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 13:03:44 +0200
Subject: [PATCH] [AMDGPU] New RegBankSelect: Add missing S/VGPR pointer types
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/142602
There's quite a few opcodes that do not care about the exact AS of the pointer,
just its size.
Adding generic types for these will help reduce duplication in the rule
definitions.
I also moved the usual B ty
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142600?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142604?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/142604
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https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/142601
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/142604
>From f9141055a09fc376354f901932b0a39e28d58c35 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 3 Jun 2025 15:08:06 +0200
Subject: [PATCH 1/2] [AMDGPU] New RegBankSelect: Add rules for `G_PTRTOINT`
and `G_I
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
Pierre-vh wrote:
ping
https://github.com/llvm/llvm-project/pull/141590
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Pierre-vh wrote:
@petar-avramovic If this is good, can you approve it so I can land it once all
other patches are approved? Thanks :)
https://github.com/llvm/llvm-project/pull/142602
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Pierre-vh wrote:
ping
https://github.com/llvm/llvm-project/pull/142601
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Pierre-vh wrote:
### Merge activity
* **Jun 19, 7:48 AM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/142603).
https://github.com/llvm/llvm-project/pull/142603
__
Pierre-vh wrote:
### Merge activity
* **Jun 19, 7:48 AM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/142602).
https://github.com/llvm/llvm-project/pull/142602
__
Pierre-vh wrote:
### Merge activity
* **Jun 19, 7:48 AM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/142601).
https://github.com/llvm/llvm-project/pull/142601
__
Pierre-vh wrote:
### Merge activity
* **Jun 19, 7:48 AM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/142604).
https://github.com/llvm/llvm-project/pull/142604
__
https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/142789
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@@ -137,7 +138,109 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::pair tryMatchRALFromUnmerge(Register Src) {
+MachineInstr *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGP
@@ -203,7 +205,14 @@ class AMDGPURegBankLegalizeCombiner {
bool tryEliminateReadAnyLane(MachineInstr &Copy) {
Register Dst = Copy.getOperand(0).getReg();
Register Src = Copy.getOperand(1).getReg();
-if (!Src.isVirtual())
+
+// Skip non-vgpr Dst
+if ((Dst.i
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
@@ -2160,7 +2160,22 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr
addrspace(1) %out, <2 x flo
; IEEE-GOODFREXP-NEXT:[[TMP38:%.*]] = insertelement <2 x float> poison,
float [[TMP27]], i64 0
; IEEE-GOODFREXP-NEXT:[[MD_1ULP_UNDEF:%.*]] = insertelement <2 x float
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145484?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 76be3031e6f1195263d63fd09d2f0087a7f5e853 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 10a9e08e314dcb5a57fd1c6a6e818a4146ed9210 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 76be3031e6f1195263d63fd09d2f0087a7f5e853 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 10a9e08e314dcb5a57fd1c6a6e818a4146ed9210 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
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