[llvm-branch-commits] [mlir] a11869c - Revert "[mlir] Make remove-dead-values pass remove blocks arguments first (#1…"

Author: lonely eagle Date: 2025-11-06T18:46:46+08:00 New Revision: a11869ccf13d99f3559a4b244dfe2c8593db783a URL: https://github.com/llvm/llvm-project/commit/a11869ccf13d99f3559a4b244dfe2c8593db783a DIFF: https://github.com/llvm/llvm-project/commit/a11869ccf13d99f3559a4b244dfe2c8593db783a.diff

[llvm-branch-commits] [llvm] [AMDGPU] Add wave reduce intrinsics for float types - 2 (PR #161815)

@@ -5330,11 +5330,13 @@ static uint32_t getIdentityValueFor32BitWaveReduction(unsigned Opc) { case AMDGPU::S_MAX_U32: return std::numeric_limits::min(); case AMDGPU::S_MAX_I32: + case AMDGPU::V_SUB_F32_e64: // +0.0 jmmartinez wrote: I haven't thought

[llvm-branch-commits] [llvm] [AMDGPU] Add wave reduce intrinsics for float types - 2 (PR #161815)

@@ -5330,11 +5330,13 @@ static uint32_t getIdentityValueFor32BitWaveReduction(unsigned Opc) { case AMDGPU::S_MAX_U32: return std::numeric_limits::min(); case AMDGPU::S_MAX_I32: + case AMDGPU::V_SUB_F32_e64: // +0.0 jmmartinez wrote: This doesn't seem

[llvm-branch-commits] [clang] [AMDGPU] Add builtins for wave reduction intrinsics (PR #161816)

https://github.com/jmmartinez approved this pull request. https://github.com/llvm/llvm-project/pull/161816 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Initial implementation for `enableMemCmpExpansion` hook (PR #166526)

zhaoqi5 wrote: > How does this optimization affect the benchmark? For example > `llvm-test-suite/MicroBenchmarks/MemFunctions`. Add some test results to help > with comparison and code review. It might be necessary to test the data under > various conditions, including different vector widths

[llvm-branch-commits] [clang] [AMDGPU] Add builtins for wave reduction intrinsics (PR #161816)

https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/161816 >From 0e9bcce2647a3adc91bc049dfc5761cbeefa19b1 Mon Sep 17 00:00:00 2001 From: Aaditya Date: Tue, 30 Sep 2025 11:37:42 +0530 Subject: [PATCH] [AMDGPU] Add builtins for wave reduction intrinsics --- clang/in

[llvm-branch-commits] [llvm] [AMDGPU] Remove named-barrier LDS lowering logic from amdgpu-lower-module-lds (PR #166731)

https://github.com/skc7 edited https://github.com/llvm/llvm-project/pull/166731 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Enable amdgpu-lower-exec-sync pass in pipeline (PR #165746)

https://github.com/skc7 edited https://github.com/llvm/llvm-project/pull/165746 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Remove named-barrier LDS lowering logic from amdgpu-lower-module-lds (PR #166731)

https://github.com/skc7 ready_for_review https://github.com/llvm/llvm-project/pull/166731 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Remove named-barrier LDS lowering logic from amdgpu-lower-module-lds (PR #166731)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Chaitanya (skc7) Changes This PR removes the named-barrier LDS lowering from `amdgpu-lower-module-lds` pass, since it is now handled by `amdgpu-lower-exec-sync` pass This PR is 3rd one in the stack. PR1 : https://github.com/llvm/

[llvm-branch-commits] [clang] [NFC][HIP] Add __builtin_*_load_lds type check test cases (PR #165388)

https://github.com/ranapratap55 approved this pull request. https://github.com/llvm/llvm-project/pull/165388 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [HIP][AMDGPU] Remove 't' from all __builtin_*_load_lds builtins (PR #165389)

https://github.com/ranapratap55 approved this pull request. https://github.com/llvm/llvm-project/pull/165389 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [IR] Add CallBr intrinsics support (PR #133907)

ro-i wrote: wait, does github now finally have the reopen feature https://github.com/llvm/llvm-project/pull/133907 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commi

[llvm-branch-commits] [llvm] [IR] Add CallBr intrinsics support (PR #133907)

https://github.com/ro-i reopened https://github.com/llvm/llvm-project/pull/133907 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoongArch] Initial implementation for `enableMemCmpExpansion` hook (PR #166526)

llvmbot wrote: @llvm/pr-subscribers-backend-loongarch Author: ZhaoQi (zhaoqi5) Changes After overriding `TargetTransformInfo::enableMemCmpExpansion` in this commit, `MergeICmps` and `ExpandMemCmp` passes will be enabled on LoongArch. --- Patch is 220.23 KiB, truncated to 20.00 KiB below

[llvm-branch-commits] [compiler-rt][sanitizers] Mark three tests as unsupported on Android (PR #166639)

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/166639 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt][sanitizers] Mark three tests as unsupported on Android (PR #166639)

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/166639 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [IR] Add CallBr intrinsics support (PR #133907)

https://github.com/ro-i closed https://github.com/llvm/llvm-project/pull/133907 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [IR] Add CallBr intrinsics support (PR #133907)

ro-i wrote: Hm, somehow github decided to automatically close this PR after I just merged the PR down the stack. Will reopen https://github.com/llvm/llvm-project/pull/133907 ___ llvm-branch-commits mailing list [email protected] https

[llvm-branch-commits] [llvm] [AMDGPU] Enable amdgpu-lower-exec-sync pass in pipeline (PR #165746)

https://github.com/skc7 updated https://github.com/llvm/llvm-project/pull/165746 >From ca4b858851a2b6c2a0e81fe6d48618332d18ca15 Mon Sep 17 00:00:00 2001 From: skc7 Date: Thu, 30 Oct 2025 22:42:33 +0530 Subject: [PATCH 1/4] [AMDGPU] Enable amdgpu-lower-special-lds pass in pipeline --- .../AMDGP

[llvm-branch-commits] [llvm] [AMDGPU] Remove named-barrier LDS lowering logic from amdgpu-lower-module-lds (PR #166731)

https://github.com/skc7 created https://github.com/llvm/llvm-project/pull/166731 This PR removes the named-barrier LDS lowering from `amdgpu-lower-module-lds` pass, since it is now handled by `amdgpu-lower-exec-sync` pass >From 0a2e9ee17ea82a7cb3fe191626ee84b05c37be83 Mon Sep 17 00:00:00 2001 F

[llvm-branch-commits] [clang] [AMDGPU] Add builtins for wave reduction intrinsics (PR #161816)

https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/161816 >From 62867d1bcdb3d8d0eba2b04a78f61f98b92e7de6 Mon Sep 17 00:00:00 2001 From: Aaditya Date: Tue, 30 Sep 2025 11:37:42 +0530 Subject: [PATCH] [AMDGPU] Add builtins for wave reduction intrinsics --- clang/in

[llvm-branch-commits] [llvm] [AMDGPU] Add wave reduce intrinsics for float types - 2 (PR #161815)

https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/161815 >From 27c0f126455f8249b7eda83b5ef900bc6d07de52 Mon Sep 17 00:00:00 2001 From: Aaditya Date: Mon, 29 Sep 2025 18:58:10 +0530 Subject: [PATCH] [AMDGPU] Add wave reduce intrinsics for float types - 2 Supported

[llvm-branch-commits] [llvm] [AMDGPU] Add wave reduce intrinsics for float types - 2 (PR #161815)

https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/161815 >From 27c0f126455f8249b7eda83b5ef900bc6d07de52 Mon Sep 17 00:00:00 2001 From: Aaditya Date: Mon, 29 Sep 2025 18:58:10 +0530 Subject: [PATCH] [AMDGPU] Add wave reduce intrinsics for float types - 2 Supported

[llvm-branch-commits] [llvm] [CI] Make premerge_advisor_explain write comments (PR #166605)

https://github.com/DavidSpickett edited https://github.com/llvm/llvm-project/pull/166605 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [mlir] [mlir][vector] Simplify createReadOrMaskedRead (PR #163736)

https://github.com/banach-space closed https://github.com/llvm/llvm-project/pull/163736 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/21.x: [RISCV] Correct the CFA offsets for stack probing. (#166616) (PR #166783)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/166783 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/21.x: [RISCV] Correct the CFA offsets for stack probing. (#166616) (PR #166783)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/166783 Backport ff11b93bb8f5578c9eb7296160570ea001a1155f Requested by: @topperc >From c343ce6d630b0c5819fbe50fec76de0408789112 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 6 Nov 2025 07:09:52 -0800 Subject:

[llvm-branch-commits] [llvm] release/21.x: [RISCV] Correct the CFA offsets for stack probing. (#166616) (PR #166783)

llvmbot wrote: @kito-cheng What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/166783 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/li

[llvm-branch-commits] [llvm] release/21.x: [RISCV] Correct the CFA offsets for stack probing. (#166616) (PR #166783)

llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: None (llvmbot) Changes Backport ff11b93bb8f5578c9eb7296160570ea001a1155f Requested by: @topperc --- Full diff: https://github.com/llvm/llvm-project/pull/166783.diff 2 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVFra

[llvm-branch-commits] [llvm] [MLIR][Python] Update Nanobind Warnings List for clang-cl on Windows (PR #166828)

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/166828 >From bc870644188ae13da4141efdf75eab0137ddcc30 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Thu, 6 Nov 2025 19:05:09 + Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20change

[llvm-branch-commits] [MLIR][Python] Update Nanobind Warnings List for clang-cl on Windows (PR #166828)

boomanaiden154 wrote: > This thing is a perennial PITA. I'm stamping to unblock but can you can also > try https://github.com/wjakob/nanobind/pull/868. Yeah, looks like it. Very interesting to see a project that is pretty against disabling warnings, but also against accepting patches to fix wa

[llvm-branch-commits] [llvm] [MLIR][Python] Update Nanobind Warnings List for clang-cl on Windows (PR #166828)

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/166828 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [ConstantTime][RISCV] Add comprehensive tests for ct.select (PR #166708)

https://github.com/wizardengineer updated https://github.com/llvm/llvm-project/pull/166708 >From 7aec58aa6f8029c514857a755b5a381e6a6b22af Mon Sep 17 00:00:00 2001 From: wizardengineer Date: Wed, 5 Nov 2025 11:01:00 -0500 Subject: [PATCH] [ConstantTime][RISCV] Add comprehensive tests for ct.sele

[llvm-branch-commits] [llvm] CodeGen: Handle bundled instructions in two-address-instructions pass (PR #166212)

nhaehnle wrote: > Have you considered the case where the instructions inside the bundle have > two uses of RegB, but only one of them is tied with RegA? I think it is > almost impossible to handle that optimally given only the summarised > information that you get from the operands of the BUND

[llvm-branch-commits] [llvm] CodeGen: Handle bundled instructions in two-address-instructions pass (PR #166212)

@@ -1665,6 +1665,22 @@ void TwoAddressInstructionImpl::processTiedPairs(MachineInstr *MI, // by SubRegB is compatible with RegA with no subregister. So regardless of // whether the dest oper writes a subreg, the source oper should not. MO.setSubReg(0); + +// Up

[llvm-branch-commits] [llvm] CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (PR #166213)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166213 From 69ff9c0f0dd1af8333d4b160003d7f8a6eea61aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 7 Oct 2025 12:17:02 -0700 Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of

[llvm-branch-commits] [llvm] CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (PR #166213)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166213 From 69ff9c0f0dd1af8333d4b160003d7f8a6eea61aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 7 Oct 2025 12:17:02 -0700 Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of

[llvm-branch-commits] [llvm] CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (PR #166213)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166213 From 69ff9c0f0dd1af8333d4b160003d7f8a6eea61aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 7 Oct 2025 12:17:02 -0700 Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of

[llvm-branch-commits] [llvm] CodeGen: Handle bundled instructions in two-address-instructions pass (PR #166212)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166212 From b6bf0c47fd34efff8a4df14df69eb1f06785 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 23 Sep 2025 19:08:52 -0700 Subject: [PATCH] CodeGen: Handle bundled instructions in two

[llvm-branch-commits] [llvm] CodeGen: Handle bundled instructions in two-address-instructions pass (PR #166212)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166212 From b6bf0c47fd34efff8a4df14df69eb1f06785 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 23 Sep 2025 19:08:52 -0700 Subject: [PATCH] CodeGen: Handle bundled instructions in two

[llvm-branch-commits] [llvm] CodeGen: Handle bundled instructions in two-address-instructions pass (PR #166212)

@@ -1665,6 +1665,22 @@ void TwoAddressInstructionImpl::processTiedPairs(MachineInstr *MI, // by SubRegB is compatible with RegA with no subregister. So regardless of // whether the dest oper writes a subreg, the source oper should not. MO.setSubReg(0); + +// Up

[llvm-branch-commits] [llvm] CodeGen: Handle bundled instructions in two-address-instructions pass (PR #166212)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp -

[llvm-branch-commits] [llvm] CodeGen: Handle bundled instructions in two-address-instructions pass (PR #166212)

https://github.com/jayfoad approved this pull request. Seems OK on the understanding that it is slightly experimental, and after some more experience we may need to change things and/or nail down the exact rules for what cases are and are not supported. https://github.com/llvm/llvm-project/pul

[llvm-branch-commits] [llvm] CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (PR #166213)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166213 From 2ca173d4a9a8a59304a5915e7b46ce46ea5c0bf7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 7 Oct 2025 12:17:02 -0700 Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of

[llvm-branch-commits] [llvm] CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (PR #166213)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166213 From 2ca173d4a9a8a59304a5915e7b46ce46ea5c0bf7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 7 Oct 2025 12:17:02 -0700 Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of

[llvm-branch-commits] [llvm] CodeGen: Handle bundled instructions in two-address-instructions pass (PR #166212)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166212 From 1224dba5fcb35911c3e80f0a734394d2ce0cd640 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 23 Sep 2025 19:08:52 -0700 Subject: [PATCH] CodeGen: Handle bundled instructions in two

[llvm-branch-commits] [llvm] CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (PR #166213)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166213 From 2ca173d4a9a8a59304a5915e7b46ce46ea5c0bf7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 7 Oct 2025 12:17:02 -0700 Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of

[llvm-branch-commits] [llvm] CodeGen: Handle bundled instructions in two-address-instructions pass (PR #166212)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166212 From 1224dba5fcb35911c3e80f0a734394d2ce0cd640 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 23 Sep 2025 19:08:52 -0700 Subject: [PATCH] CodeGen: Handle bundled instructions in two

[llvm-branch-commits] [llvm] CodeGen: Handle bundled instructions in two-address-instructions pass (PR #166212)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166212 From 1224dba5fcb35911c3e80f0a734394d2ce0cd640 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 23 Sep 2025 19:08:52 -0700 Subject: [PATCH] CodeGen: Handle bundled instructions in two

[llvm-branch-commits] [llvm] [CI] Make premerge_advisor_explain write comments (PR #166605)

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/166605 >From 06c030dcb4ee57be287beffd96d1b21ef1697dd4 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Wed, 5 Nov 2025 18:23:46 + Subject: [PATCH] fix Created using spr 1.3.7 --- .ci/premerge_advisor_ex

[llvm-branch-commits] [CI] Make premerge upload/write comments (PR #166609)

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/166609 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [CI] Make premerge upload/write comments (PR #166609)

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/166609 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CI] Make premerge_advisor_explain write comments (PR #166605)

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/166605 >From 06c030dcb4ee57be287beffd96d1b21ef1697dd4 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Wed, 5 Nov 2025 18:23:46 + Subject: [PATCH] fix Created using spr 1.3.7 --- .ci/premerge_advisor_ex

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #148900)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148900 >From 429dfd75797bfb24e208266cab1fbc14fc79c717 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:03:15 -0400 Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector AtomicExpan

[llvm-branch-commits] [llvm] [X86] Cast atomic vectors in IR to support floats (PR #148899)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148899 >From 4d1cdadc3259ed811a186b049bb1589ebc4e5470 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:02:04 -0400 Subject: [PATCH] [X86] Cast atomic vectors in IR to support floats This commit casts float

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #148900)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148900 >From 429dfd75797bfb24e208266cab1fbc14fc79c717 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:03:15 -0400 Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector AtomicExpan

[llvm-branch-commits] [llvm] [X86] Cast atomic vectors in IR to support floats (PR #148899)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148899 >From 4d1cdadc3259ed811a186b049bb1589ebc4e5470 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:02:04 -0400 Subject: [PATCH] [X86] Cast atomic vectors in IR to support floats This commit casts float

[llvm-branch-commits] [llvm] [SelectionDAG] Split vector types for atomic load (PR #165818)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/165818 >From 94119264a0fd461b3cb18d6dbd30337f274e403b Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 30 Oct 2025 12:19:59 -0400 Subject: [PATCH] [SelectionDAG] Split vector types for atomic load Vector types that aren'

[llvm-branch-commits] [MLIR][Python] Update Nanobind Warnings List for clang-cl on Windows (PR #166828)

llvmbot wrote: @llvm/pr-subscribers-mlir Author: Aiden Grossman (boomanaiden154) Changes We recently moved over to compiling with clang-cl on Windows. This ended up causing a large increase in warnings, particularly due to how warnings are handled in nanobind. cd91d0fff9293a904704784c92c28

[llvm-branch-commits] [MLIR][Python] Update Nanobind Warnings List for clang-cl on Windows (PR #166828)

https://github.com/boomanaiden154 created https://github.com/llvm/llvm-project/pull/166828 We recently moved over to compiling with clang-cl on Windows. This ended up causing a large increase in warnings, particularly due to how warnings are handled in nanobind. cd91d0fff9293a904704784c92c28637b

[llvm-branch-commits] [llvm] [CI] Make premerge_advisor_explain write comments (PR #166605)

@@ -12,6 +12,94 @@ certifi==2025.8.3 \ --hash=sha256:e564105f78ded564e3ae7c923924435e1daa7463faeab5bb932bc53ffae63407 \ --hash=sha256:f6c12493cfb1b06ba2ff328595af9350c65d6644968e5d3a2ffd78699af217a5 # via requests +cffi==2.0.0 \ + --hash=sha256:00bdf7acc5f7951

[llvm-branch-commits] [llvm] [BOLT] Move call probe information to CallSiteInfo (PR #165490)

https://github.com/rafaelauler approved this pull request. https://github.com/llvm/llvm-project/pull/165490 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CI] Make premerge_advisor_explain write comments (PR #166605)

@@ -45,13 +83,31 @@ def main(commit_sha: str, build_log_files: list[str]): ) if advisor_response.status_code == 200: print(advisor_response.json()) +comments = [ +get_comment( +github_token, +pr_number, +

[llvm-branch-commits] [llvm] [BOLT] Move call probe information to CallSiteInfo (PR #165490)

https://github.com/aaupov closed https://github.com/llvm/llvm-project/pull/165490 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lldb] release/21.x: [lldb] Implement DW_CFA_val_offset and DW_CFA_val_offset_sf (#150732) (PR #166611)

https://github.com/JDevlieghere approved this pull request. https://github.com/llvm/llvm-project/pull/166611 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [MLIR][Python] Update Nanobind Warnings List for clang-cl on Windows (PR #166828)

https://github.com/makslevental approved this pull request. This thing is a perennial PITA. I'm stamping to unblock but can you can also try [NB_SUPPRESS_WARNINGS](https://github.com/wjakob/nanobind/pull/868). https://github.com/llvm/llvm-project/pull/166828

[llvm-branch-commits] [MLIR][Python] Update Nanobind Warnings List for clang-cl on Windows (PR #166828)

makslevental wrote: PS also this https://github.com/wjakob/nanobind/issues/994 🙂 https://github.com/llvm/llvm-project/pull/166828 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/ll

[llvm-branch-commits] [llvm] [CI] Make premerge_advisor_explain write comments (PR #166605)

https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/166605 >From 06c030dcb4ee57be287beffd96d1b21ef1697dd4 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Wed, 5 Nov 2025 18:23:46 + Subject: [PATCH 1/2] fix Created using spr 1.3.7 --- .ci/premerge_adviso

[llvm-branch-commits] [llvm] [CI] Make premerge_advisor_explain write comments (PR #166605)

@@ -4,20 +4,58 @@ """Script for getting explanations from the premerge advisor.""" import argparse -import os import platform import sys +import json import requests +import github +import github.PullRequest import generate_test_report_lib PREMERGE_ADVISOR_URL = (

[llvm-branch-commits] [llvm] [SelectionDAG] Split vector types for atomic load (PR #165818)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/165818 >From 1434bcf8d9be03eeabce92430d00e02b0e434069 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 30 Oct 2025 12:19:59 -0400 Subject: [PATCH] [SelectionDAG] Split vector types for atomic load Vector types that aren'

[llvm-branch-commits] [llvm] [X86] Remove extra MOV after widening atomic load (PR #148898)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148898 >From b92b6dac8913654dc0ba987ce328c47fa7330778 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:01:24 -0400 Subject: [PATCH] [X86] Remove extra MOV after widening atomic load This change adds patter

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #148900)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148900 >From a657bd946e7be59892a00a447ca7018d0715c6a5 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:03:15 -0400 Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector AtomicExpan

[llvm-branch-commits] [llvm] [SelectionDAG] Split vector types for atomic load (PR #165818)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/165818 >From 1434bcf8d9be03eeabce92430d00e02b0e434069 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 30 Oct 2025 12:19:59 -0400 Subject: [PATCH] [SelectionDAG] Split vector types for atomic load Vector types that aren'

[llvm-branch-commits] [llvm] [X86] Cast atomic vectors in IR to support floats (PR #148899)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148899 >From f9b99b992450687c7da5048c82e9ce38efc3ff1d Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:02:04 -0400 Subject: [PATCH] [X86] Cast atomic vectors in IR to support floats This commit casts float

[llvm-branch-commits] [llvm] [X86] Cast atomic vectors in IR to support floats (PR #148899)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148899 >From f9b99b992450687c7da5048c82e9ce38efc3ff1d Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:02:04 -0400 Subject: [PATCH] [X86] Cast atomic vectors in IR to support floats This commit casts float

[llvm-branch-commits] [llvm] [X86] Remove extra MOV after widening atomic load (PR #148898)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148898 >From b92b6dac8913654dc0ba987ce328c47fa7330778 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:01:24 -0400 Subject: [PATCH] [X86] Remove extra MOV after widening atomic load This change adds patter

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #148900)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148900 >From a657bd946e7be59892a00a447ca7018d0715c6a5 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:03:15 -0400 Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector AtomicExpan

[llvm-branch-commits] [llvm] CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (PR #166213)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166213 From dd8c2ece4a1287580cec17fff56e8eaa314ffef7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 7 Oct 2025 12:17:02 -0700 Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of

[llvm-branch-commits] [llvm] CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (PR #166213)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166213 From cc06ca25470188cc8e767eab72fcfe83958cf4b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 7 Oct 2025 12:17:02 -0700 Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of

[llvm-branch-commits] [llvm] CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (PR #166213)

@@ -4088,7 +4107,20 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI, LV->getVarInfo(DefReg).AliveBlocks.clear(); } -if (LIS) { +if (MI.isBundle()) { + VirtRegInfo VRI = AnalyzeVirtRegInBundle(MI, DefReg); + if (!VRI.Reads &&

[llvm-branch-commits] [llvm] CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (PR #166213)

https://github.com/nhaehnle updated https://github.com/llvm/llvm-project/pull/166213 From cc06ca25470188cc8e767eab72fcfe83958cf4b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 7 Oct 2025 12:17:02 -0700 Subject: [PATCH] CodeGen/AMDGPU: Allow 3-address conversion of

[llvm-branch-commits] [llvm] [X86] Remove extra MOV after widening atomic load (PR #148898)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/148898 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [CI][NFC] Refactor compute_platform_title into generate_test_report_lib (PR #166604)

https://github.com/Keenuts approved this pull request. https://github.com/llvm/llvm-project/pull/166604 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [CI] Add Ability to Explain Failures (PR #166590)

https://github.com/Keenuts edited https://github.com/llvm/llvm-project/pull/166590 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [CI] Add Ability to Explain Failures (PR #166590)

https://github.com/Keenuts approved this pull request. a small thing, otherwise LGTM (modulus test coverage request by David) https://github.com/llvm/llvm-project/pull/166590 ___ llvm-branch-commits mailing list [email protected] https

[llvm-branch-commits] [CI] Add Ability to Explain Failures (PR #166590)

@@ -82,16 +93,29 @@ def find_failure_in_ninja_logs(ninja_logs: list[list[str]]) -> list[tuple[str, s return failures -def _format_failures(failures: list[tuple[str, str]]) -> list[str]: +def _format_failures( +failures: list[tuple[str, str]], failure_explanations: di

[llvm-branch-commits] [mlir] [mlir][vector] Simplify createReadOrMaskedRead (PR #163736)

https://github.com/banach-space reopened https://github.com/llvm/llvm-project/pull/163736 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/21.x: [RISCV] Correct the CFA offsets for stack probing. (#166616) (PR #166783)

https://github.com/ilovepi approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/166783 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CI] Make premerge_advisor_explain write comments (PR #166605)

@@ -33,17 +33,18 @@ function at-exit { # If building fails there will be no results files. shopt -s nullglob - if [[ "$GITHUB_STEP_SUMMARY" != "" ]]; then + if [[ "$GITHUB_ACTIONS" != "" ]]; then boomanaiden154 wrote: This checks that we are running in

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #148900)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148900 >From 242cf54a6b527e573c4d30a3bea47e3a458fb8c1 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:03:15 -0400 Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector AtomicExpan

[llvm-branch-commits] [llvm] [SelectionDAG] Split vector types for atomic load (PR #165818)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/165818 >From 8466578444bc27c0d8c5dc2ee95f074a96b5e47f Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 30 Oct 2025 12:19:59 -0400 Subject: [PATCH] [SelectionDAG] Split vector types for atomic load Vector types that aren'

[llvm-branch-commits] [llvm] [AtomicExpand] Add bitcasts when expanding load atomic vector (PR #148900)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148900 >From 242cf54a6b527e573c4d30a3bea47e3a458fb8c1 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:03:15 -0400 Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector AtomicExpan

[llvm-branch-commits] [llvm] [X86] Cast atomic vectors in IR to support floats (PR #148899)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148899 >From 23fb9283f42bd418afb4d478dfaa7215c4d16093 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:02:04 -0400 Subject: [PATCH] [X86] Cast atomic vectors in IR to support floats This commit casts float

[llvm-branch-commits] [llvm] [X86] Cast atomic vectors in IR to support floats (PR #148899)

https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/148899 >From 23fb9283f42bd418afb4d478dfaa7215c4d16093 Mon Sep 17 00:00:00 2001 From: jofrn Date: Tue, 15 Jul 2025 13:02:04 -0400 Subject: [PATCH] [X86] Cast atomic vectors in IR to support floats This commit casts float

[llvm-branch-commits] [llvm] [ConstantTime][RISCV] Add comprehensive tests for ct.select (PR #166708)

https://github.com/wizardengineer ready_for_review https://github.com/llvm/llvm-project/pull/166708 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [ConstantTime][WebAssembly] Add comprehensive tests for ct.select (PR #166709)

https://github.com/wizardengineer ready_for_review https://github.com/llvm/llvm-project/pull/166709 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [ConstantTime][Clang] Add __builtin_ct_select for constant-time selection (PR #166703)

https://github.com/wizardengineer ready_for_review https://github.com/llvm/llvm-project/pull/166703 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [ConstantTime] Native ct.select support for ARM32 and Thumb (PR #166707)

https://github.com/wizardengineer ready_for_review https://github.com/llvm/llvm-project/pull/166707 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [ConstantTime] Native ct.select support for X86 and i386 (PR #166704)

https://github.com/wizardengineer ready_for_review https://github.com/llvm/llvm-project/pull/166704 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

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