[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: prevent false positives due to jump tables (PR #138884)

https://github.com/atrosinenko updated https://github.com/llvm/llvm-project/pull/138884 >From f568ed034b0d9d91654f842653cd7260fe6d773d Mon Sep 17 00:00:00 2001 From: Anatoly Trosinenko Date: Tue, 6 May 2025 11:31:03 +0300 Subject: [PATCH] [BOLT] Gadget scanner: prevent false positives due to ju

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

@@ -0,0 +1,58 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// +// Test optimization pipelines do not interfere with AllocToken lowering, and we +// pass on function attributes correctly. +// +// RUN: %clang_cc1 -fsa

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

@@ -0,0 +1,58 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// +// Test optimization pipelines do not interfere with AllocToken lowering, and we +// pass on function attributes correctly. +// +// RUN: %clang_cc1 -fsa

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

@@ -0,0 +1,52 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 zmodem wrote: Same here, I'd suggest writing the checks by hand. Only the call instructions are interesting (especially their metadata), so I t

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

@@ -0,0 +1,58 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// +// Test optimization pipelines do not interfere with AllocToken lowering, and we +// pass on function attributes correctly. +// +// RUN: %clang_cc1 -fsa

[llvm-branch-commits] [lldb] release/21.x: [LLDB][ProcessWindows] Set exit status on instance rather than going through all targets (#159308) (PR #161541)

DavidSpickett wrote: * This removes a significant lag when quitting lldb on Windows. * The code change is basically "do the same thing with fewer steps", very low risk. I was able to review by just looking at the code paths. * We've not had any instability on Windows on Arm, or reports of instab

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

@@ -0,0 +1,58 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// +// Test optimization pipelines do not interfere with AllocToken lowering, and we +// pass on function attributes correctly. +// +// RUN: %clang_cc1 -fsa

[llvm-branch-commits] [llvm] [AArch64][SME] Reshuffle emit[prologue|epilogue]() for splitSVEObjects (NFCI) (PR #161217)

https://github.com/sdesmalen-arm approved this pull request. https://github.com/llvm/llvm-project/pull/161217 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

https://github.com/melver updated https://github.com/llvm/llvm-project/pull/156839 >From b3653330c2c39ebaa094670f11afb0f9d36b9de2 Mon Sep 17 00:00:00 2001 From: Marco Elver Date: Thu, 4 Sep 2025 12:07:26 +0200 Subject: [PATCH] fixup! Insert AllocToken into index.rst Created using spr 1.3.8-bet

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

@@ -0,0 +1,52 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 melver wrote: Switched back to hand-written tests. https://github.com/llvm/llvm-project/pull/156839 ___

[llvm-branch-commits] [llvm] release/21.x: [Hexagon] Add opcode V6_vS32Ub_npred_ai for offset validity check (#161618) (PR #161692)

llvmbot wrote: @androm3da What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/161692 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/lis

[llvm-branch-commits] [llvm] release/21.x: [Hexagon] Add opcode V6_vS32Ub_npred_ai for offset validity check (#161618) (PR #161692)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/161692 Backport daa4e57ccf38ff6ac22243e98a035c87b9f9f3ae Requested by: @androm3da >From 220bac16a417e97bf97fdcb34855e28b2e6dfdf7 Mon Sep 17 00:00:00 2001 From: Ikhlas Ajbar Date: Thu, 2 Oct 2025 09:43:24 -0500 Subjec

[llvm-branch-commits] [llvm] release/21.x: [Hexagon] Add opcode V6_vS32Ub_npred_ai for offset validity check (#161618) (PR #161692)

llvmbot wrote: @llvm/pr-subscribers-backend-hexagon Author: None (llvmbot) Changes Backport daa4e57ccf38ff6ac22243e98a035c87b9f9f3ae Requested by: @androm3da --- Full diff: https://github.com/llvm/llvm-project/pull/161692.diff 2 Files Affected: - (modified) llvm/lib/Target/Hexagon/Hex

[llvm-branch-commits] [llvm] release/21.x: [Hexagon] Add opcode V6_vS32Ub_npred_ai for offset validity check (#161618) (PR #161692)

https://github.com/androm3da approved this pull request. https://github.com/llvm/llvm-project/pull/161692 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/21.x: [Hexagon] Add opcode V6_vS32Ub_npred_ai for offset validity check (#161618) (PR #161692)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/161692 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

https://github.com/melver updated https://github.com/llvm/llvm-project/pull/156839 >From b3653330c2c39ebaa094670f11afb0f9d36b9de2 Mon Sep 17 00:00:00 2001 From: Marco Elver Date: Thu, 4 Sep 2025 12:07:26 +0200 Subject: [PATCH] fixup! Insert AllocToken into index.rst Created using spr 1.3.8-bet

[llvm-branch-commits] [llvm] [AMDGPU] Update code sequence for CU-mode Release Fences in GFX10+ (PR #161638)

Pierre-vh wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161638?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [llvm] [AMDGPU] Update code sequence for CU-mode Release Fences in GFX10+ (PR #161638)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Pierre van Houtryve (Pierre-vh) Changes They were previously optimized to not emit any waitcnt, which is technically correct because there is no reordering of operations at workgroup scope in CU mode for GFX10+. This breaks tran

[llvm-branch-commits] [llvm] [AArch64][SME] Support split ZPR and PPR area allocation (PR #142392)

https://github.com/sdesmalen-arm approved this pull request. Thanks @MacDue, LGTM! https://github.com/llvm/llvm-project/pull/142392 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/

[llvm-branch-commits] [AllocToken, Clang] Infer type hints from sizeof expressions and casts (PR #156841)

@@ -1353,6 +1354,92 @@ void CodeGenFunction::EmitAllocToken(llvm::CallBase *CB, QualType AllocType) { CB->setMetadata(llvm::LLVMContext::MD_alloc_token, MDN); } +/// Infer type from a simple sizeof expression. +static QualType inferTypeFromSizeofExpr(const Expr *E) { + con

[llvm-branch-commits] [clang] [CIR] Upstream `AddressSpace` conversions support (PR #161212)

https://github.com/RiverDave edited https://github.com/llvm/llvm-project/pull/161212 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [flang] [mlir] [mlir][omp] Improve canonloop/iv naming (PR #159773)

Meinersbur wrote: > The reduction and privatisation declaration operations have multiple regions. They are "[IsolatedFromAbove](https://mlir.llvm.org/docs/Traits/#isolatedfromabove)" though, meaning each indivually have they separated namespace. This also meant that I previously misunderstool

[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

@@ -0,0 +1,301 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 zmodem wrote: For the record, I'm not against auto-generated tests in general. But for these tests, the auto-generated versions looked a lot l

[llvm-branch-commits] [llvm] CodeGen: Stop checking for physregs in constrainRegClass (PR #161795)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/161795 It's nonsensical to call this function on a physical register. >From 2833da98821c20e651468e63ef834acfa66cac88 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 3 Oct 2025 14:00:55 +0900 Subject: [PATCH] C

[llvm-branch-commits] [llvm] [LoongArch] Custom legalize vector_shuffle to `xvinsve0.{w/d}` when possible (PR #161156)

zhaoqi5 wrote: Same as https://github.com/llvm/llvm-project/pull/160857 which has been closed because of my silly mistake. https://github.com/llvm/llvm-project/pull/161156 ___ llvm-branch-commits mailing list [email protected] https:/

[llvm-branch-commits] [llvm] [llvm][mustache] Use single pass when tokenizing (PR #159196)

https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/159196 >From 709be29237e8bab16b3d7f4703cc4127ca7f59fc Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Mon, 15 Sep 2025 23:27:50 -0700 Subject: [PATCH] [llvm][mustache] Use single pass when tokenizing The old implement

[llvm-branch-commits] [llvm] AMDGPU: Remove LDS_DIRECT_CLASS register class (PR #161762)

https://github.com/rampitec requested changes to this pull request. Same here: drop mir tests which test what tablegen has generated. https://github.com/llvm/llvm-project/pull/161762 ___ llvm-branch-commits mailing list [email protected]

[llvm-branch-commits] [llvm] MIRVocabulary changes (PR #161713)

svkeerthy wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161713?utm_source=stack-comment-downstack-mergeability-warning

[llvm-branch-commits] [clang] [llvm] [clang][SPARC] Pass 16-aligned structs with the correct alignment in CC (PR #161766)

llvmbot wrote: @llvm/pr-subscribers-clang-codegen Author: Brad Smith (brad0) Changes Pad argument registers to preserve overaligned structs in LLVM IR. Additionally, since i128 values will be lowered as split i64 pairs in the backend, correctly set the alignment of such arguments as 16 byt

[llvm-branch-commits] [clang] [llvm] [clang][SPARC] Pass 16-aligned structs with the correct alignment in CC (PR #161766)

https://github.com/brad0 updated https://github.com/llvm/llvm-project/pull/161766 >From 9ee4ac8a83592385794978cd15fa094d926cca2c Mon Sep 17 00:00:00 2001 From: Koakuma Date: Thu, 2 Oct 2025 22:22:07 -0400 Subject: [PATCH] [clang][SPARC] Pass 16-aligned structs with the correct alignment in CC

[llvm-branch-commits] [clang] [llvm] [clang][SPARC] Pass 16-aligned structs with the correct alignment in CC (#155829) (PR #161766)

https://github.com/brad0 edited https://github.com/llvm/llvm-project/pull/161766 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [CIR] Upstream `AddressSpace` conversions support (PR #161212)

https://github.com/RiverDave updated https://github.com/llvm/llvm-project/pull/161212 >From baaea0b9d214bd5940f4b16909d47f491918c584 Mon Sep 17 00:00:00 2001 From: David Rivera Date: Mon, 29 Sep 2025 11:05:44 -0400 Subject: [PATCH 1/4] [CIR] Upstream AddressSpace casting support --- .../CIR/D

[llvm-branch-commits] [clang] [CIR] Upstream `AddressSpace` conversions support (PR #161212)

RiverDave wrote: I updated this based on the recent feedback on #161028 I made a change tn the function: `performAddrSpaceCast` and I opted for getting rid of the `LangAS` parameters for both source and destination, there’s to main reasons: 1. They were redundant and not utilized. 2. In [OG

[llvm-branch-commits] [llvm] [AMDGPU][SIInsertWaitCnts] De-duplicate code (NFC) (PR #161161)

https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/161161 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][SIInsertWaitCnts] Remove redundant TII/TRI/MRI arguments (NFC) (PR #161357)

https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/161357 >From 73c43575873aa2bc3dfc051a49bb05fc4fc99ca9 Mon Sep 17 00:00:00 2001 From: pvanhout Date: Mon, 29 Sep 2025 12:24:57 +0200 Subject: [PATCH] [AMDGPU][SIInsertWaitCnts] Remove redundant TII/TRI/MRI arguments

[llvm-branch-commits] [llvm] [AArch64][SME] Support split ZPR and PPR area allocation (PR #142392)

@@ -531,6 +538,10 @@ bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const { if (!EnableRedZone) return false; + const AArch64FunctionInfo *AFI = MF.getInfo(); + if (AFI->hasSplitSVEObjects()) +return false; + sdesmalen-arm wro

[llvm-branch-commits] [clang] [CIR] Upstream `AddressSpace` conversions support (PR #161212)

@@ -172,28 +190,21 @@ RValue CIRGenFunction::emitBuiltinExpr(const GlobalDecl &gd, unsigned builtinID, builder.getUInt8Ty(), "bi_alloca", suitableAlignmentInBytes, size); // Initialize the allocated buffer if required. -if (builtinID != Builtin::BI__builtin_al

[llvm-branch-commits] [clang] [CIR] Upstream `AddressSpace` conversions support (PR #161212)

https://github.com/RiverDave updated https://github.com/llvm/llvm-project/pull/161212 >From baaea0b9d214bd5940f4b16909d47f491918c584 Mon Sep 17 00:00:00 2001 From: David Rivera Date: Mon, 29 Sep 2025 11:05:44 -0400 Subject: [PATCH 1/4] [CIR] Upstream AddressSpace casting support --- .../CIR/D

[llvm-branch-commits] [llvm] [AMDGPU][MC] Avoid creating lit64() operands unless asked or needed. (PR #161191)

https://github.com/kosarev ready_for_review https://github.com/llvm/llvm-project/pull/161191 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [clang][SPARC] Pass 16-aligned structs with the correct alignment in CC (PR #161766)

llvmbot wrote: @llvm/pr-subscribers-clang Author: Brad Smith (brad0) Changes Pad argument registers to preserve overaligned structs in LLVM IR. Additionally, since i128 values will be lowered as split i64 pairs in the backend, correctly set the alignment of such arguments as 16 bytes. Thi

[llvm-branch-commits] [clang] [llvm] [clang][SPARC] Pass 16-aligned structs with the correct alignment in CC (PR #161766)

llvmbot wrote: @llvm/pr-subscribers-backend-sparc Author: Brad Smith (brad0) Changes Pad argument registers to preserve overaligned structs in LLVM IR. Additionally, since i128 values will be lowered as split i64 pairs in the backend, correctly set the alignment of such arguments as 16 byt

[llvm-branch-commits] [llvm] AMDGPU: Remove LDS_DIRECT_CLASS register class (PR #161762)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/161762 This is a singleton register class which is a bad idea, and not actually used. >From 628c706149875d7ca11df6bf3cfb76a7571591b9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 3 Oct 2025 10:21:10 +0900 Su

[llvm-branch-commits] [llvm] AMDGPU: Remove LDS_DIRECT_CLASS register class (PR #161762)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes This is a singleton register class which is a bad idea, and not actually used. --- Patch is 88.23 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/161762.

[llvm-branch-commits] [llvm] AMDGPU: Remove LDS_DIRECT_CLASS register class (PR #161762)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161762?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [llvm] [clang][SPARC] Pass 16-aligned structs with the correct alignment in CC (PR #161766)

https://github.com/brad0 created https://github.com/llvm/llvm-project/pull/161766 Pad argument registers to preserve overaligned structs in LLVM IR. Additionally, since i128 values will be lowered as split i64 pairs in the backend, correctly set the alignment of such arguments as 16 bytes. This

[llvm-branch-commits] [clang] [llvm] [clang][SPARC] Pass 16-aligned structs with the correct alignment in CC (PR #161766)

https://github.com/brad0 milestoned https://github.com/llvm/llvm-project/pull/161766 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64][SME] Support split ZPR and PPR area allocation (PR #142392)

@@ -2277,6 +2351,70 @@ void AArch64FrameLowering::determineStackHazardSlot( << StackHazardSize << "\n"); AFI->setStackHazardSlotIndex(ID); } + + // Determine if we should use SplitSVEObjects. This should only be used if + // there's a possibility o

[llvm-branch-commits] [clang] [CIR] Upstream `AddressSpace` conversions support (PR #161212)

https://github.com/RiverDave deleted https://github.com/llvm/llvm-project/pull/161212 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [flang] [llvm] [mlir] [openmp] [Flang] Add standalone tile support (PR #160298)

https://github.com/Meinersbur updated https://github.com/llvm/llvm-project/pull/160298 >From bfe9c6b642ebc01f113dbf0a574e424e83f7162a Mon Sep 17 00:00:00 2001 From: Michael Kruse Date: Tue, 23 Sep 2025 15:33:52 +0200 Subject: [PATCH 1/4] [flang] Add standalone tile support --- flang/lib/Lower

[llvm-branch-commits] [llvm] DAG: Remove TargetLowering::checkForPhysRegDependency (PR #161787)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/161787 I have no idea why this was here. The only implementation was AMDGPU, which was essentially repeating the generic logic but for one specific case. >From 2d6ea1f0f59ad06eef7fd4f87522a76e9544bb00 Mon Sep 17 00:00:0

[llvm-branch-commits] [llvm] DAG: Remove TargetLowering::checkForPhysRegDependency (PR #161787)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161787?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] DAG: Remove TargetLowering::checkForPhysRegDependency (PR #161787)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/161787 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Remove TargetLowering::checkForPhysRegDependency (PR #161787)

llvmbot wrote: @llvm/pr-subscribers-llvm-regalloc Author: Matt Arsenault (arsenm) Changes I have no idea why this was here. The only implementation was AMDGPU, which was essentially repeating the generic logic but for one specific case. --- Full diff: https://github.com/llvm/llvm-project/

[llvm-branch-commits] [llvm] AMDGPU: Stop trying to constrain register class of post-RA-pseudos (PR #161792)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/161792 This is trying to constrain the register class of a physical register, which makes no sense. >From cf04ae0c7c664d2fba2995eae7ce825fa4badd95 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 3 Oct 2025 14:

[llvm-branch-commits] [llvm] AMDGPU: Fix trying to constrain physical registers in spill handling (PR #161793)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes It's nonsensical to call constrainRegClass on a physical register, and we should not see virtual registers here. --- Full diff: https://github.com/llvm/llvm-project/pull/161793.diff 2 Files Affect

[llvm-branch-commits] [llvm] AMDGPU: Fix constrain register logic for physregs (PR #161794)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes We do not need to reconstrain physical registers. Enables an additional fold for constant physregs. --- Patch is 260.21 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llv

[llvm-branch-commits] [llvm] AMDGPU: Stop trying to constrain register class of post-RA-pseudos (PR #161792)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161792?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Stop trying to constrain register class of post-RA-pseudos (PR #161792)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/161792 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] CodeGen: Stop checking for physregs in constrainRegClass (PR #161795)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161795?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] CodeGen: Stop checking for physregs in constrainRegClass (PR #161795)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/161795 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Fix constrain register logic for physregs (PR #161794)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/161794 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

@@ -0,0 +1,301 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 zmodem wrote: I think it would be clearer to hand-write the test, focused entirely on the call instructions and their metadata. https://githu

[llvm-branch-commits] [llvm] [LV] Bundle partial reductions inside VPExpressionRecipe (PR #147302)

@@ -2955,12 +2966,14 @@ tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red, // Match reduce.add(mul(ext, ext)). if (RecipeA && RecipeB && -(RecipeA->getOpcode() == RecipeB->getOpcode() || A == B) && +(RecipeA->getOpcode() == RecipeB->getO

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

@@ -0,0 +1,58 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 zmodem wrote: I would suggest hand-writing the expectations instead, to make it more clear what are actually the interesting bits being checked

[llvm-branch-commits] [llvm] [AMDGPU] Update code sequence for CU-mode Release Fences in GFX10+ (PR #161638)

github-actions[bot] wrote: :warning: undef deprecator found issues in your code. :warning: You can test this locally with the following command: ``bash git diff -U0 --pickaxe-regex -S '([^a-zA-Z0-9#_-]undef[^a-zA-Z0-9_-]|UndefValue::get)' 'HEAD~1' HEAD llvm/lib/Target/AMDGPU/SIM

[llvm-branch-commits] [llvm] [AMDGPU] Update code sequence for CU-mode Release Fences in GFX10+ (PR #161638)

https://github.com/Pierre-vh ready_for_review https://github.com/llvm/llvm-project/pull/161638 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [Clang] Introduce -fsanitize=alloc-token (PR #156839)

@@ -0,0 +1,58 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// +// Test optimization pipelines do not interfere with AllocToken lowering, and we +// pass on function attributes correctly. +// +// RUN: %clang_cc1 -fsa

[llvm-branch-commits] [AllocToken, Clang] Infer type hints from sizeof expressions and casts (PR #156841)

@@ -1353,6 +1354,92 @@ void CodeGenFunction::EmitAllocToken(llvm::CallBase *CB, QualType AllocType) { CB->setMetadata(llvm::LLVMContext::MD_alloc_token, MDN); } +/// Infer type from a simple sizeof expression. +static QualType inferTypeFromSizeofExpr(const Expr *E) { + con

[llvm-branch-commits] [llvm] Greedy: Move physreg check when trying to recolor vregs (NFC) (PR #160484)

https://github.com/qcolombet approved this pull request. Good catch! https://github.com/llvm/llvm-project/pull/160484 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-co

[llvm-branch-commits] [llvm] Greedy: Use initializer list for recoloring candidates (NFC) (PR #160486)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/160486 >From f6250bed3d3b224fc5c7a4110e35e1c3c6d416c4 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 24 Sep 2025 19:14:06 +0900 Subject: [PATCH] Greedy: Use initializer list for recoloring candidates (NFC) --

[llvm-branch-commits] [llvm] Greedy: Take hints from copy to physical subreg (PR #160467)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/160467 >From 9604dab28900f63fce615c31f5f624b031a94fcd Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 24 Sep 2025 16:53:33 +0900 Subject: [PATCH] Greedy: Take hints from copy to physical subreg Previously this

[llvm-branch-commits] [llvm] Greedy: Take hints from copy to physical subreg (PR #160467)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/160467 >From 9604dab28900f63fce615c31f5f624b031a94fcd Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 24 Sep 2025 16:53:33 +0900 Subject: [PATCH] Greedy: Take hints from copy to physical subreg Previously this

[llvm-branch-commits] [llvm] Greedy: Use initializer list for recoloring candidates (NFC) (PR #160486)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/160486 >From f6250bed3d3b224fc5c7a4110e35e1c3c6d416c4 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 24 Sep 2025 19:14:06 +0900 Subject: [PATCH] Greedy: Use initializer list for recoloring candidates (NFC) --

[llvm-branch-commits] [llvm] Greedy: Merge VirtRegMap queries into one use (NFC) (PR #160485)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/160485 >From 585006d84dcf14f95d91ed48bc9f528e649b3261 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 24 Sep 2025 19:06:39 +0900 Subject: [PATCH] Greedy: Merge VirtRegMap queries into one use (NFC) --- llvm/l

[llvm-branch-commits] [llvm] [llvm][mustache] Avoid extra allocations in parseSection (PR #159199)

https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/159199 >From f93d7387c377d5247b7b819c60524f983059b963 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Tue, 16 Sep 2025 09:40:04 -0700 Subject: [PATCH] [llvm][mustache] Avoid extra allocations in parseSection We don't

[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

@@ -0,0 +1,301 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 vitalybuka wrote: Short term on review - yes, long term it's just unnecessary pain to update them https://github.com/llvm/llvm-project/pull/15

[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

https://github.com/vitalybuka edited https://github.com/llvm/llvm-project/pull/156840 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

https://github.com/vitalybuka approved this pull request. I'd prefer this patch LLVM only, and clang goes into the next patch https://github.com/llvm/llvm-project/pull/156840 ___ llvm-branch-commits mailing list [email protected] https

[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

@@ -69,19 +69,30 @@ enum class TokenMode : unsigned { /// Token ID based on allocated type hash. TypeHash = 2, + + /// Token ID based on allocated type hash, where the top half ID-space is + /// reserved for types that contain pointers and the bottom half for types + //

[llvm-branch-commits] [llvm] [IR2Vec] Refactor MIR vocabulary to use opcode-based indexing (PR #161713)

https://github.com/svkeerthy ready_for_review https://github.com/llvm/llvm-project/pull/161713 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [AllocToken, Clang] Implement TypeHashPointerSplit mode (PR #156840)

@@ -0,0 +1,301 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 melver wrote: I dunno what the right answer is here - for the .ll tests, definitely auto-generated, for .cpp/.c tests I'm unsure. The Clang au

[llvm-branch-commits] [llvm] [llvm][mustache] Use StringRef parameters (PR #159190)

https://github.com/evelez7 edited https://github.com/llvm/llvm-project/pull/159190 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] bdb8b2b - Revert "[HLSL] Update Frontend to support version 1.2 of root signature (#160…"

Author: joaosaffran Date: 2025-10-02T16:45:31-04:00 New Revision: bdb8b2b33ce4ec74802b83e8189cb5d56a112231 URL: https://github.com/llvm/llvm-project/commit/bdb8b2b33ce4ec74802b83e8189cb5d56a112231 DIFF: https://github.com/llvm/llvm-project/commit/bdb8b2b33ce4ec74802b83e8189cb5d56a112231.diff L

[llvm-branch-commits] [llvm] [PowerPC] Implement paddis (PR #161572)

https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/161572 >From 012b638031fb72d36525234115f9d7b87d8c98e3 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Tue, 30 Sep 2025 18:09:31 + Subject: [PATCH 1/3] [PowerPC] Implement paddis --- .../Target/PowerPC/AsmParser/PPC

[llvm-branch-commits] [llvm] 220bac1 - [Hexagon] Add opcode V6_vS32Ub_npred_ai for offset validity check (#161618)

Author: Ikhlas Ajbar Date: 2025-10-02T15:58:31Z New Revision: 220bac16a417e97bf97fdcb34855e28b2e6dfdf7 URL: https://github.com/llvm/llvm-project/commit/220bac16a417e97bf97fdcb34855e28b2e6dfdf7 DIFF: https://github.com/llvm/llvm-project/commit/220bac16a417e97bf97fdcb34855e28b2e6dfdf7.diff LOG:

[llvm-branch-commits] [llvm] release/21.x: [Hexagon] Add opcode V6_vS32Ub_npred_ai for offset validity check (#161618) (PR #161692)

https://github.com/dyung closed https://github.com/llvm/llvm-project/pull/161692 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/21.x: [Hexagon] Add opcode V6_vS32Ub_npred_ai for offset validity check (#161618) (PR #161692)

github-actions[bot] wrote: @androm3da (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR.

[llvm-branch-commits] [llvm] [IR2Vec] Refactor MIR vocabulary to use opcode-based indexing (PR #161713)

https://github.com/svkeerthy edited https://github.com/llvm/llvm-project/pull/161713 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] port 5b4819e to release (PR #159209)

dwblaikie wrote: > Hi @dwblaikie, before I merge your change into the release branch, can you > confirm that the premerge failures in libcxx were not caused by your change > here? So far as I can tell, yeah, they seem unrelated. @ldionne - any idea what's going on with libcxx presubmit checks

[llvm-branch-commits] [llvm] [PowerPC] Implement paddis (PR #161572)

https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/161572 >From 012b638031fb72d36525234115f9d7b87d8c98e3 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Tue, 30 Sep 2025 18:09:31 + Subject: [PATCH 1/2] [PowerPC] Implement paddis --- .../Target/PowerPC/AsmParser/PPC

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Handle branch weights in `simplifySwitchLookup` (PR #161739)

https://github.com/mtrofin created https://github.com/llvm/llvm-project/pull/161739 None >From 1b6920213b57235b62daf431f11cce74f3b5a5c3 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Wed, 1 Oct 2025 17:08:48 -0700 Subject: [PATCH] [SimplifyCFG][profcheck] Handle branch weights in `simplif

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Handle branch weights in `simplifySwitchLookup` (PR #161739)

llvmbot wrote: @llvm/pr-subscribers-llvm-transforms Author: Mircea Trofin (mtrofin) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/161739.diff 2 Files Affected: - (modified) llvm/lib/Transforms/Utils/SimplifyCFG.cpp (+18-4) - (modified) llvm/test/Transforms/Simplify

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Handle branch weights in `simplifySwitchLookup` (PR #161739)

https://github.com/mtrofin ready_for_review https://github.com/llvm/llvm-project/pull/161739 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Handle branch weights in `simplifySwitchLookup` (PR #161739)

mtrofin wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/161739?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] [SimplifyCFG][profcheck] Handle branch weights in `simplifySwitchLookup` (PR #161739)

https://github.com/mtrofin updated https://github.com/llvm/llvm-project/pull/161739 >From 24ab181f625ab0dc4fe7953034312551f50a4189 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Wed, 1 Oct 2025 17:08:48 -0700 Subject: [PATCH] [SimplifyCFG][profcheck] Handle branch weights in `simplifySwitc

[llvm-branch-commits] [llvm] [llvm][mustache] Refactor template rendering (PR #159189)

https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/159189 >From 7ca57bb5bfcf4c257bea3f77e39c042e5e482435 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Fri, 12 Sep 2025 00:06:14 -0700 Subject: [PATCH] [llvm][mustache] Refactor template rendering Move the rendering lo

[llvm-branch-commits] [llvm] [llvm][mustache] Optimize accessor splitting with a single pass (PR #159198)

https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/159198 >From 66ea253c076cffb6aaf6569806c7b32c069e754d Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Tue, 16 Sep 2025 00:24:43 -0700 Subject: [PATCH] [llvm][mustache] Optimize accessor splitting with a single pass T

[llvm-branch-commits] [llvm] release/21.x: [NVPTX] Disable relative lookup tables (#159748) (PR #160064)

github-actions[bot] wrote: @nikic (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. htt

[llvm-branch-commits] [llvm] [llvm][mustache] Avoid redundant saves in accessor splitting (PR #159197)

https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/159197 >From c6534b6ad31f12f8050be911df89961b5596499b Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Tue, 16 Sep 2025 00:11:47 -0700 Subject: [PATCH] [llvm][mustache] Avoid redundant saves in accessor splitting The s

[llvm-branch-commits] [clang] [CIR] Upstream AddressSpace casting support (PR #161212)

https://github.com/RiverDave updated https://github.com/llvm/llvm-project/pull/161212 >From a6313408ef8e8f9ad129e39cb0d8d0f2fb2f0ee3 Mon Sep 17 00:00:00 2001 From: David Rivera Date: Mon, 29 Sep 2025 11:05:44 -0400 Subject: [PATCH] [CIR] Upstream AddressSpace casting support --- .../CIR/Diale

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