Author: MaheshRavishankar
Date: 2025-09-18T09:29:29-07:00
New Revision: 7af3f6e0317e84900e6683ac0ea3dc60b805904e
URL:
https://github.com/llvm/llvm-project/commit/7af3f6e0317e84900e6683ac0ea3dc60b805904e
DIFF:
https://github.com/llvm/llvm-project/commit/7af3f6e0317e84900e6683ac0ea3dc60b805904e.d
https://github.com/vpykhtin updated
https://github.com/llvm/llvm-project/pull/150937
>From ae3589e2c93351349cd1bbb5586c2dfcb075ea68 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Thu, 10 Apr 2025 11:58:13 +
Subject: [PATCH] amdgpu_use_ssaupdaterbulk_in_structurizecfg
---
llvm/lib/Tra
https://github.com/RossBrunton converted_to_draft
https://github.com/llvm/llvm-project/pull/157651
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https://github.com/joaosaffran updated
https://github.com/llvm/llvm-project/pull/153287
>From b1e34ff07fffe96fec438b87027bd2c450b6b36f Mon Sep 17 00:00:00 2001
From: Joao Saffran <{ID}+{username}@users.noreply.github.com>
Date: Tue, 12 Aug 2025 13:07:42 -0700
Subject: [PATCH 01/24] adding valida
@@ -47,74 +47,61 @@ static func::FuncOp getOrDeclare(fir::FirOpBuilder
&builder, Location loc,
return func;
}
-static bool isZero(Value v) {
- if (auto cst = v.getDefiningOp())
-if (auto attr = dyn_cast(cst.getValue()))
- return attr.getValue().isZero();
- return
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156840
>From 14c75441e84aa32e4f5876598b9a2c59d4ecbe65 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 21:32:21 +0200
Subject: [PATCH 1/2] fixup! fix for incomplete types
Created using spr 1.3.8-beta.1
https://github.com/tobias-stadler updated
https://github.com/llvm/llvm-project/pull/156715
>From d33b31f01aeeb9005581b0a2a1f21c898463aa02 Mon Sep 17 00:00:00 2001
From: Tobias Stadler
Date: Thu, 18 Sep 2025 12:34:55 +0100
Subject: [PATCH 1/3] Replace bitstream blobs by yaml
Created using spr 1
https://github.com/kparzysz created
https://github.com/llvm/llvm-project/pull/159632
Since ODS doesn't store a list of OmpObjects (i.e. not as OmpObjectList), some
semantics-checking functions needed to be updated to operate on a single object
at a time.
>From 7bb9fb5b3b9a2dfcd1d00f01c86fe26c
llvmbot wrote:
@llvm/pr-subscribers-flang-semantics
Author: Krzysztof Parzyszek (kparzysz)
Changes
Since ODS doesn't store a list of OmpObjects (i.e. not as OmpObjectList), some
semantics-checking functions needed to be updated to operate on a single object
at a time.
---
Full diff: htt
@@ -1070,8 +1070,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "namespace llvm {\n";
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
<< " explicit " << ClassName
- << "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode = ~0u, "
-
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/159641?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/mtrofin created
https://github.com/llvm/llvm-project/pull/159645
None
>From 92728fa5d41bd5f6ef63837bcb3ea8e85b7a8764 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Mon, 15 Sep 2025 17:49:18 +
Subject: [PATCH] [profcheck][SimplifyCFG] Propagate !prof from `switch` to
https://github.com/mtrofin edited
https://github.com/llvm/llvm-project/pull/159645
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@@ -1,5 +1,5 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=simplifycfg
-simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --ch
github-actions[bot] wrote:
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https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/159645
>From 6d3342f397d39e366a06eb6bcabddec0b3d5a963 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Mon, 15 Sep 2025 17:49:18 +
Subject: [PATCH] [profcheck][SimplifyCFG] Propagate !prof from `switch` to
`sele
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/159641
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https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/159655
>From 108bf356e743d36b4eb5d0217720cf47ab85f33f Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Thu, 18 Sep 2025 14:31:38 -0700
Subject: [PATCH 1/2] [HLSL] NonUniformResourceIndex implementation
Adds HLSL funct
https://github.com/mtrofin approved this pull request.
https://github.com/llvm/llvm-project/pull/158376
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158274
>From 7d3e2fa03f76098b2f4f90a2c4407e18d59423c5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 9 Sep 2025 11:15:47 +0900
Subject: [PATCH] X86: Switch to RegClassByHwMode
Replace the target uses of Point
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158271
>From e7ef891fb2c4e21bec4d23af954ad9204f3eb48f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 8 Sep 2025 14:04:59 +0900
Subject: [PATCH] SPARC: Use RegClassByHwMode instead of PointerLikeRegClass
---
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158274
>From 7d3e2fa03f76098b2f4f90a2c4407e18d59423c5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 9 Sep 2025 11:15:47 +0900
Subject: [PATCH] X86: Switch to RegClassByHwMode
Replace the target uses of Point
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158273
>From 5b8f38bb56b46b9e63fe2031f9b43e4bbba333fb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 6 Sep 2025 21:14:45 +0900
Subject: [PATCH 1/3] Mips: Switch to RegClassByHwMode
---
.../Target/Mips/AsmPar
https://github.com/s-barannikov approved this pull request.
LGTM
Is there a reason to not implement the renaming suggestion? (Like it would
require renaming methods in C++ files or so or make the naming inconsistent.)
https://github.com/llvm/llvm-project/pull/158777
https://github.com/s-barannikov edited
https://github.com/llvm/llvm-project/pull/158777
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s-barannikov wrote:
They seem all lowercase to me :man_shrugging:
```
$ grep -E ": (Register)?Operand" llvm/lib/Target/PowerPC/*.td | cut -d ':' -f
2,3
def s16imm64 : Operand {
def u16imm64 : Operand {
def s17imm64 : Operand {
def tocentry : Operand {
def tlsreg : Operand {
def tlsgd : Operand
https://github.com/s-barannikov approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/158271
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arsenm wrote:
Most of the operands seem capitalized
https://github.com/llvm/llvm-project/pull/158777
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@@ -211,6 +211,21 @@ def FeatureUseIndirectJumpsHazard :
SubtargetFeature<"use-indirect-jump-hazard",
def FeatureStrictAlign
: SubtargetFeature<"strict-align", "StrictAlign", "true",
"Disable unaligned load store for r6">;
+//===-
@@ -916,6 +916,30 @@ DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned
RegNo, uint64_t Address,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
s-barannikov wrote:
Can you add a comment why
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158777
>From 0e5dfd5493a599e6eb9e5a0a0b21cd542c964e8f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 5 Sep 2025 18:03:59 +0900
Subject: [PATCH 1/3] PPC: Replace PointerLikeRegClass with RegClassByHwMode
---
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158271
>From e7ef891fb2c4e21bec4d23af954ad9204f3eb48f Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 8 Sep 2025 14:04:59 +0900
Subject: [PATCH] SPARC: Use RegClassByHwMode instead of PointerLikeRegClass
---
https://github.com/s-barannikov approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/158273
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@@ -46,20 +46,8 @@ unsigned MipsRegisterInfo::getPICCallReg() { return
Mips::T9; }
const TargetRegisterClass *
MipsRegisterInfo::getPointerRegClass(unsigned Kind) const {
- MipsPtrClass PtrClassKind = static_cast(Kind);
-
- switch (PtrClassKind) {
- case MipsPtrClass::Defa
mtrofin wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/159645?utm_source=stack-comment-downstack-mergeability-warning";
@@ -301,12 +380,16 @@ class Vocabulary {
constexpr static unsigned NumCanonicalEntries =
MaxOpcodes + MaxCanonicalTypeIDs + MaxOperandKinds + MaxPredicateKinds;
- // Base offsets for slot layout to simplify index computation
+ // Base offsets for flat index computati
@@ -1272,6 +1272,57 @@ void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E,
llvm::Value *Bound,
EmitCheck(std::make_pair(Check, CheckKind), CheckHandler, StaticData, Index);
}
+static bool
+typeContainsPointer(QualType T,
+llvm::SmallPtrSet &VisitedR
@@ -261,55 +262,106 @@ void FlowAwareEmbedder::computeEmbeddings(const
BasicBlock &BB) const {
BBVecMap[&BB] = BBVector;
}
+//
==--===//
+// VocabStorage
+//===-
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llvmbot wrote:
@llvm/pr-subscribers-backend-hexagon
Author: Matt Arsenault (arsenm)
Changes
Both conceptually belong to the same subtarget, so it should not
be necessary to pass in the context TargetRegisterInfo to any
TargetInstrInfo member. Add this reference so those superfluous
argumen
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156841
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/158273
>From 5b8f38bb56b46b9e63fe2031f9b43e4bbba333fb Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 6 Sep 2025 21:14:45 +0900
Subject: [PATCH 1/3] Mips: Switch to RegClassByHwMode
---
.../Target/Mips/AsmPar
https://github.com/ergawy updated
https://github.com/llvm/llvm-project/pull/156589
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https://github.com/llvm/llvm-project/pull/158278
>From 96a4d9030b00b30f6aa7d9a70b191c1aaab1f2e8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 12 Sep 2025 20:45:56 +0900
Subject: [PATCH] AMDGPU: Stop using aligned VGPR classes for addRegisterClass
Th
https://github.com/melver edited
https://github.com/llvm/llvm-project/pull/156842
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@@ -3352,10 +3352,15 @@ class CodeGenFunction : public CodeGenTypeCache {
SanitizerAnnotateDebugInfo(ArrayRef
Ordinals,
SanitizerHandler Handler);
- /// Emit additional metadata used by the AllocToken instrumentation.
+ /// Emit metadata used
@@ -5760,6 +5764,24 @@ bool Sema::BuiltinAllocaWithAlign(CallExpr *TheCall) {
return false;
}
+bool Sema::BuiltinAllocTokenInfer(CallExpr *TheCall) {
melver wrote:
I'm indifferent here. Switching to a static function.
https://github.com/llvm/llvm-project/p
joker-eph wrote:
> > That isn't in MLIR right now, so that's not generally usable.
>
> I've added `complex.powi -> complex.pow` conversion to the
> `ComplexToStandard` MLIR pass.
Thanks, LG!
https://github.com/llvm/llvm-project/pull/158722
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deaklajos wrote:
@vitalybuka
https://github.com/llvm/llvm-project/pull/159551
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nikic wrote:
The diff here is fairly large, but also very mechanical. This fixes a
regression for the Rust defmt crate with LLVM 21.
https://github.com/llvm/llvm-project/pull/159420
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https://github.com/efriedma-quic commented:
Can you split "implement basic codegen support for prefalign" (the bits which
don't depend on the .prefalign directive) into a separate patch? It's not
clear what's causing the test changes here.
https://github.com/llvm/llvm-project/pull/155529
github-actions[bot] wrote:
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https://github.com/tobias-stadler updated
https://github.com/llvm/llvm-project/pull/156715
>From d33b31f01aeeb9005581b0a2a1f21c898463aa02 Mon Sep 17 00:00:00 2001
From: Tobias Stadler
Date: Thu, 18 Sep 2025 12:34:55 +0100
Subject: [PATCH 1/2] Replace bitstream blobs by yaml
Created using spr 1
https://github.com/MacDue updated
https://github.com/llvm/llvm-project/pull/142391
>From 0dfb0725e2a4f82af47821946bfbbfcd7ed08e10 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell
Date: Thu, 8 May 2025 17:38:27 +
Subject: [PATCH] [AArch64] Prepare for split ZPR and PPR area allocation
(NFCI)
https://github.com/vzakhari commented:
LGTM with some final comments.
https://github.com/llvm/llvm-project/pull/158722
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@@ -1272,7 +1272,18 @@ mlir::Value genMathOp(fir::FirOpBuilder &builder,
mlir::Location loc,
LLVM_DEBUG(llvm::dbgs() << "Generating '" << mathLibFuncName
<< "' operation with type ";
mathLibFuncType.dump(); llvm::dbgs() << "\n");
@@ -175,12 +176,20 @@ PowIStrengthReduction::matchAndRewrite(
Value one;
Type opType = getElementTypeOrSelf(op.getType());
- if constexpr (std::is_same_v)
+ if constexpr (std::is_same_v) {
one = arith::ConstantOp::create(rewriter, loc,
https://github.com/vzakhari edited
https://github.com/llvm/llvm-project/pull/158722
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/158246
This is special for the same reason av_mov_b64_imm_pseudo is special.
>From e5032294b4979c4b7f2367cee30c24d42901714b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 5 Sep 2025 17:27:37 +0900
Subject: [P
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/158224
Both conceptually belong to the same subtarget, so it should not
be necessary to pass in the context TargetRegisterInfo to any
TargetInstrInfo member. Add this reference so those superfluous
arguments can be remov
https://github.com/mgorny milestoned
https://github.com/llvm/llvm-project/pull/157848
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https://github.com/TIFitis updated
https://github.com/llvm/llvm-project/pull/158722
>From 6976910364aa2fe18603aefcb27b10bd0120513d Mon Sep 17 00:00:00 2001
From: Akash Banerjee
Date: Mon, 15 Sep 2025 20:35:29 +0100
Subject: [PATCH 1/7] Add complex.powi op.
---
flang/lib/Optimizer/Builder/Intr
@@ -1272,7 +1272,18 @@ mlir::Value genMathOp(fir::FirOpBuilder &builder,
mlir::Location loc,
LLVM_DEBUG(llvm::dbgs() << "Generating '" << mathLibFuncName
<< "' operation with type ";
mathLibFuncType.dump(); llvm::dbgs() << "\n");
@@ -175,12 +176,20 @@ PowIStrengthReduction::matchAndRewrite(
Value one;
Type opType = getElementTypeOrSelf(op.getType());
- if constexpr (std::is_same_v)
+ if constexpr (std::is_same_v) {
one = arith::ConstantOp::create(rewriter, loc,
https://github.com/jdenny-ornl edited
https://github.com/llvm/llvm-project/pull/157754
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@@ -1274,6 +1274,12 @@ def AllocaWithAlignUninitialized : Builtin {
let Prototype = "void*(size_t, _Constant size_t)";
}
+def AllocTokenInfer : Builtin {
+ let Spellings = ["__builtin_alloc_token_infer"];
melver wrote:
Renaming to __builtin_infer_alloc_tok
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156840
>From 14c75441e84aa32e4f5876598b9a2c59d4ecbe65 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 21:32:21 +0200
Subject: [PATCH 1/2] fixup! fix for incomplete types
Created using spr 1.3.8-beta.1
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156842
>From 48227c8f7712b2dc807b252d18353c91905b1fb5 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 17:19:04 +0200
Subject: [PATCH] fixup!
Created using spr 1.3.8-beta.1
---
llvm/lib/Transforms/Inst
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156842
>From 48227c8f7712b2dc807b252d18353c91905b1fb5 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Mon, 8 Sep 2025 17:19:04 +0200
Subject: [PATCH] fixup!
Created using spr 1.3.8-beta.1
---
llvm/lib/Transforms/Inst
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156841
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https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156839
>From b3653330c2c39ebaa094670f11afb0f9d36b9de2 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Thu, 4 Sep 2025 12:07:26 +0200
Subject: [PATCH] fixup! Insert AllocToken into index.rst
Created using spr 1.3.8-bet
https://github.com/melver updated
https://github.com/llvm/llvm-project/pull/156839
>From b3653330c2c39ebaa094670f11afb0f9d36b9de2 Mon Sep 17 00:00:00 2001
From: Marco Elver
Date: Thu, 4 Sep 2025 12:07:26 +0200
Subject: [PATCH] fixup! Insert AllocToken into index.rst
Created using spr 1.3.8-bet
https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/159258
>From e1a23dd6e31734b05af239bb827a280d403564ee Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Wed, 17 Sep 2025 10:20:46 +0800
Subject: [PATCH 1/3] [LoongArch] Generate [x]vldi instructions with special
constant
https://github.com/melver edited
https://github.com/llvm/llvm-project/pull/156841
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@@ -1349,6 +1350,98 @@ void CodeGenFunction::EmitAllocTokenHint(llvm::CallBase
*CB,
CB->setMetadata(llvm::LLVMContext::MD_alloc_token_hint, MDN);
}
+/// Infer type from a simple sizeof expression.
+static QualType inferTypeFromSizeofExpr(const Expr *E) {
+ const Expr *Arg
https://github.com/TIFitis updated
https://github.com/llvm/llvm-project/pull/158722
>From 6976910364aa2fe18603aefcb27b10bd0120513d Mon Sep 17 00:00:00 2001
From: Akash Banerjee
Date: Mon, 15 Sep 2025 20:35:29 +0100
Subject: [PATCH 1/6] Add complex.powi op.
---
flang/lib/Optimizer/Builder/Intr
https://github.com/jdenny-ornl edited
https://github.com/llvm/llvm-project/pull/159163
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https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/159258
>From e1a23dd6e31734b05af239bb827a280d403564ee Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Wed, 17 Sep 2025 10:20:46 +0800
Subject: [PATCH 1/3] [LoongArch] Generate [x]vldi instructions with special
constant
https://github.com/melver edited
https://github.com/llvm/llvm-project/pull/156842
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https://github.com/RossBrunton converted_to_draft
https://github.com/llvm/llvm-project/pull/157484
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https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From 3b0c210862015dc304004641990fea429f8e31c7 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH 1/3] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by
defau
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146074
>From b484d75cff9bd4703dd2c90d041d4df0aefd0e3c Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 26 Jun 2025 06:10:35 -0400
Subject: [PATCH 1/2] [SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145330
>From da5b337fef36cdee209845b51bba323e84272334 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 04:03:53 -0400
Subject: [PATCH 1/2] [AMDGPU][SDAG] Handle ISD::PTRADD in various special
cas
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146074
>From b484d75cff9bd4703dd2c90d041d4df0aefd0e3c Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 26 Jun 2025 06:10:35 -0400
Subject: [PATCH 1/2] [SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145330
>From da5b337fef36cdee209845b51bba323e84272334 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 04:03:53 -0400
Subject: [PATCH 1/2] [AMDGPU][SDAG] Handle ISD::PTRADD in various special
cas
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 7c417c4c1413a3807d476b7fc490256084a0ac62 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/5] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we ca
https://github.com/RossBrunton created
https://github.com/llvm/llvm-project/pull/159581
None
>From 149a8e88c447d10e9181ba0940c5d05ace6f0d5a Mon Sep 17 00:00:00 2001
From: Ross Brunton
Date: Thu, 18 Sep 2025 15:23:45 +0100
Subject: [PATCH] [Offload] Add olGetMemInfo with platform-less API
---
https://github.com/RossBrunton closed
https://github.com/llvm/llvm-project/pull/157484
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https://github.com/llvm/llvm-project/pull/157651
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>From 7c417c4c1413a3807d476b7fc490256084a0ac62 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/5] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we ca
https://github.com/melver edited
https://github.com/llvm/llvm-project/pull/156842
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https://github.com/tobias-stadler updated
https://github.com/llvm/llvm-project/pull/156715
>From d33b31f01aeeb9005581b0a2a1f21c898463aa02 Mon Sep 17 00:00:00 2001
From: Tobias Stadler
Date: Thu, 18 Sep 2025 12:34:55 +0100
Subject: [PATCH] Replace bitstream blobs by yaml
Created using spr 1.3.7
https://github.com/melver edited
https://github.com/llvm/llvm-project/pull/156842
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https://github.com/deaklajos created
https://github.com/llvm/llvm-project/pull/159551
Backports: 3fc723ec2cf1965aa4eec8883957fbbe1b2e7027 (#136195)
Ran into the issue on Alpine when building with TSAN that `__sanitizer_msghdr`
and the `msghdr` provided by musl did not match. This caused lots o
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Deák Lajos (deaklajos)
Changes
Backports: 3fc723ec2cf1965aa4eec8883957fbbe1b2e7027 (#136195)
Ran into the issue on Alpine when building with TSAN that `__sanitizer_msghdr`
and the `msghdr` provided by musl did not match. T
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