[llvm-branch-commits] [llvm] [IR] Introduce the `ptrtoaddr` instruction (PR #139357)

https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/139357 >From 25dc175562349410f161ef0e80246301d9a7ba79 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Fri, 9 May 2025 22:43:37 -0700 Subject: [PATCH] fix docs build Created using spr 1.3.6-beta.1 --- llvm/do

[llvm-branch-commits] [llvm] [IR] Introduce the `ptrtoaddr` instruction (PR #139357)

https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/139357 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sa

[llvm-branch-commits] [llvm] [IR] Introduce the `ptrtoaddr` instruction (PR #139357)

https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/139357 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sa

[llvm-branch-commits] [clang] [Clang][Backport] Fix handling of reference types in tryEvaluateBuiltinObjectSize (#138247) (PR #139579)

https://github.com/cor3ntin milestoned https://github.com/llvm/llvm-project/pull/139579 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [Clang][Backport] Fix handling of reference types in tryEvaluateBuiltinObjectSize (#138247) (PR #139579)

https://github.com/cor3ntin created https://github.com/llvm/llvm-project/pull/139579 The order of operation was slightly incorrect, as we were checking for incomplete types *before* handling reference types. Fixes #129397 - >From 814e1d2a1762edee3f04346cbcd18bd3fad23aec Mon Sep 17 00

[llvm-branch-commits] [clang] [clang][analysis] Fix flaky clang/test/Analysis/live-stmts.cpp test (2nd attempt) (#127406) (PR #139591)

llvmbot wrote: @llvm/pr-subscribers-clang-analysis Author: Balazs Benics (steakhal) Changes In my previous attempt (#126913) of fixing the flaky case was on a good track when I used the begin locations as a stable ordering. However, I forgot to consider the case when the begin locations

[llvm-branch-commits] [clang] [clang][analysis] Fix flaky clang/test/Analysis/live-stmts.cpp test (2nd attempt) (#127406) (PR #139591)

llvmbot wrote: @llvm/pr-subscribers-clang Author: Balazs Benics (steakhal) Changes In my previous attempt (#126913) of fixing the flaky case was on a good track when I used the begin locations as a stable ordering. However, I forgot to consider the case when the begin locations are the s

[llvm-branch-commits] [clang] [clang][analysis] Fix flaky clang/test/Analysis/live-stmts.cpp test (2nd attempt) (#127406) (PR #139591)

https://github.com/steakhal milestoned https://github.com/llvm/llvm-project/pull/139591 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [clang][analysis] Fix flaky clang/test/Analysis/live-stmts.cpp test (2nd attempt) (#127406) (PR #139591)

https://github.com/steakhal created https://github.com/llvm/llvm-project/pull/139591 In my previous attempt (#126913) of fixing the flaky case was on a good track when I used the begin locations as a stable ordering. However, I forgot to consider the case when the begin locations are the same

[llvm-branch-commits] [clang] [clang][analysis] Fix flaky clang/test/Analysis/live-stmts.cpp test (2nd attempt) (#127406) (PR #139591)

steakhal wrote: We decided to backport in https://github.com/llvm/llvm-project/pull/127406#issuecomment-2683679225 https://github.com/llvm/llvm-project/pull/139591 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.l

[llvm-branch-commits] [IRTranslator] Handle ptrtoaddr (PR #139601)

@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const User &U, return true; } +bool IRTranslator::translatePtrToAddr(const User &U, + MachineIRBuilder &MIRBuilder) { + if (containsBF16Type(U)) +return false;

[llvm-branch-commits] [IRTranslator] Handle ptrtoaddr (PR #139601)

@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const User &U, return true; } +bool IRTranslator::translatePtrToAddr(const User &U, + MachineIRBuilder &MIRBuilder) { + if (containsBF16Type(U)) +return false;

[llvm-branch-commits] [IRTranslator] Handle ptrtoaddr (PR #139601)

@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const User &U, return true; } +bool IRTranslator::translatePtrToAddr(const User &U, + MachineIRBuilder &MIRBuilder) { + if (containsBF16Type(U)) +return false;

[llvm-branch-commits] [AMDGPU] Set AS8 address width to 48 bits (PR #139419)

@@ -145,79 +145,79 @@ define amdgpu_ps ptr addrspace(7) @s_ptrmask_buffer_fat_ptr_i32_neg8(ptr addrspa ret ptr addrspace(7) %masked } -define ptr addrspace(8) @v_ptrmask_buffer_resource_variable_i128(ptr addrspace(8) %ptr, i128 %mask) { -; GCN-LABEL: v_ptrmask_buffer_resou

[llvm-branch-commits] [AMDGPU] Set AS8 address width to 48 bits (PR #139419)

https://github.com/krzysz00 commented: Minor note re the autoupgrade, overall this change makes sense (and it does mean that, if we can get GEP's "wrapping add on the index bits" behavior working, ptr addrspace(8)` becomes *technically* GEPable, though with the note of "be real hecking careful

[llvm-branch-commits] [AMDGPU] Set AS8 address width to 48 bits (PR #139419)

https://github.com/krzysz00 edited https://github.com/llvm/llvm-project/pull/139419 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AMDGPU] Set AS8 address width to 48 bits (PR #139419)

@@ -5773,7 +5773,7 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) { if (!DL.contains("-p7") && !DL.starts_with("p7")) Res.append("-p7:160:256:256:32"); if (!DL.contains("-p8") && !DL.starts_with("p8")) - Res.append("-p8:128:128"); +

[llvm-branch-commits] [IRTranslator] Handle ptrtoaddr (PR #139601)

@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const User &U, return true; } +bool IRTranslator::translatePtrToAddr(const User &U, + MachineIRBuilder &MIRBuilder) { + if (containsBF16Type(U)) +return false;

[llvm-branch-commits] [IRTranslator] Handle ptrtoaddr (PR #139601)

@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const User &U, return true; } +bool IRTranslator::translatePtrToAddr(const User &U, + MachineIRBuilder &MIRBuilder) { + if (containsBF16Type(U)) +return false;

[llvm-branch-commits] [IRTranslator] Handle ptrtoaddr (PR #139601)

@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const User &U, return true; } +bool IRTranslator::translatePtrToAddr(const User &U, + MachineIRBuilder &MIRBuilder) { + if (containsBF16Type(U)) +return false;

[llvm-branch-commits] [IRTranslator] Handle ptrtoaddr (PR #139601)

@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const User &U, return true; } +bool IRTranslator::translatePtrToAddr(const User &U, + MachineIRBuilder &MIRBuilder) { + if (containsBF16Type(U)) +return false;

[llvm-branch-commits] [clang] [analyzer] Workaround for slowdown spikes (unintended scope increase) (#136720) (PR #139597)

@@ -0,0 +1,200 @@ +// RUN: %clang_analyze_cc1 -analyzer-checker=core,debug.ExprInspection -verify=expected,default %s +// RUN: %clang_analyze_cc1 -analyzer-checker=core,debug.ExprInspection -analyzer-config inline-functions-with-ambiguous-loops=true -verify=expected,enabled %s

[llvm-branch-commits] [clang] [HLSL] Implicit resource binding for cbuffers (PR #139022)

https://github.com/hekota updated https://github.com/llvm/llvm-project/pull/139022 >From 8194951b52e024b78c7f148d65ce6c23b3fcf424 Mon Sep 17 00:00:00 2001 From: Helena Kotas Date: Wed, 7 May 2025 21:05:39 -0700 Subject: [PATCH 1/6] [HLSL] Implicit binding for cbuffers Constant buffers defined

[llvm-branch-commits] [AMDGPU] Set AS8 address width to 48 bits (PR #139419)

@@ -7970,17 +7970,26 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, // On arm64_32, pointers are 32 bits when stored in memory, but // zero-extended to 64 bits when in registers. Thus the mask is 32 bits to -// match the index type, but the po

[llvm-branch-commits] [AMDGPU] Set AS8 address width to 48 bits (PR #139419)

arsenm wrote: > Of the 128-bits of buffer descriptor only 48 bits are address bits, Technically true, but why not just call it 64? https://github.com/llvm/llvm-project/pull/139419 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [clang] [HLSL] Implicit resource binding for cbuffers (PR #139022)

https://github.com/hekota edited https://github.com/llvm/llvm-project/pull/139022 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Use minnum instead of maxnum for fmed3 src2-nan fold (PR #139531)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/139531?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [clang] [Clang][Backport] Demote mixed enumeration arithmetic error to a warning (#131811) (PR #139396)

https://github.com/AaronBallman approved this pull request. LGTM! https://github.com/llvm/llvm-project/pull/139396 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commi

[llvm-branch-commits] [llvm] AMDGPU: Disable most fmed3 folds for strictfp (PR #139530)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/139530.diff 2 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp (+3) - (modified) llvm/test/Transforms/

[llvm-branch-commits] [clang] release/20.x: [clang-format] Fix a crash on formatting missing r_pare… (PR #139345)

https://github.com/mydeveloperday approved this pull request. https://github.com/llvm/llvm-project/pull/139345 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139495 >From 4e01f6071209b8947ec78440f7f30ad73b38e4a8 Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 13:32:41 +0800 Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q ex

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139508 >From 867ad9de22ff26fd0e91eae2ab23ef9c9a219acb Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 15:04:28 +0800 Subject: [PATCH] [RISCV][MC] Add Q support for Zfa --- llvm/lib/Target/RI

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139495 >From 4e01f6071209b8947ec78440f7f30ad73b38e4a8 Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 13:32:41 +0800 Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q ex

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139508 >From 867ad9de22ff26fd0e91eae2ab23ef9c9a219acb Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 15:04:28 +0800 Subject: [PATCH] [RISCV][MC] Add Q support for Zfa --- llvm/lib/Target/RI

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt]; //===--===// let Predicates = [HasStdExtQ] in { - let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in - def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$r

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt]; //===--===// let Predicates = [HasStdExtQ] in { - let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in - def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$r

[llvm-branch-commits] [clang] [llvm] [HLSL] Add resource constructor with implicit binding for global resources (PR #138976)

@@ -668,6 +668,26 @@ BuiltinTypeDeclBuilder::addHandleConstructorFromBinding() { .finalize(); } +BuiltinTypeDeclBuilder & +BuiltinTypeDeclBuilder::addHandleConstructorFromImplicitBinding() { + if (Record->isCompleteDefinition()) V-FEXrt wrote: Could yo

[llvm-branch-commits] [clang] [llvm] [HLSL] Add resource constructor with implicit binding for global resources (PR #138976)

https://github.com/V-FEXrt approved this pull request. https://github.com/llvm/llvm-project/pull/138976 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [HLSL] Add resource constructor with implicit binding for global resources (PR #138976)

@@ -668,6 +668,26 @@ BuiltinTypeDeclBuilder::addHandleConstructorFromBinding() { .finalize(); } +BuiltinTypeDeclBuilder & +BuiltinTypeDeclBuilder::addHandleConstructorFromImplicitBinding() { + if (Record->isCompleteDefinition()) +return *this; + + using PH = Builti

[llvm-branch-commits] [clang] [llvm] [HLSL] Add resource constructor with implicit binding for global resources (PR #138976)

@@ -3269,27 +3285,42 @@ static bool initVarDeclWithCtor(Sema &S, VarDecl *VD, return true; } -static bool initGlobalResourceDecl(Sema &S, VarDecl *VD) { +bool SemaHLSL::initGlobalResourceDecl(VarDecl *VD) { + std::optional RegisterSlot; + uint32_t SpaceNo = 0; HLSLResou

[llvm-branch-commits] [clang] [llvm] [HLSL] Add resource constructor with implicit binding for global resources (PR #138976)

@@ -55,11 +55,33 @@ export void foo() { // CHECK-SAME: i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) // CHECK-NEXT: ret void -// Buf2 initialization part 1 - FIXME: constructor with implicit binding does not exist yet; -// the global init function currently

[llvm-branch-commits] [llvm] [BOLT][NFC] Disambiguate sample as basic/IP sample (PR #139350)

https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/139350 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-se

[llvm-branch-commits] [llvm] [BOLT][NFC] Disambiguate sample as basic/IP sample (PR #139350)

https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/139350 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-se

[llvm-branch-commits] [llvm] [BOLT] Build heatmap with pre-aggregated data (PR #138798)

https://github.com/maksfb approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/138798 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [BOLT] Build heatmap with pre-aggregated data (PR #138798)

https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/138798 >From f6b275f682c598d5c026efcbd348c6e8a35c759b Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Tue, 6 May 2025 20:09:58 -0700 Subject: [PATCH 1/2] keep parsing build-id Created using spr 1.3.4 --- bolt/lib/Pro

[llvm-branch-commits] [llvm] [BOLT] Build heatmap with pre-aggregated data (PR #138798)

https://github.com/aaupov updated https://github.com/llvm/llvm-project/pull/138798 >From f6b275f682c598d5c026efcbd348c6e8a35c759b Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Tue, 6 May 2025 20:09:58 -0700 Subject: [PATCH 1/2] keep parsing build-id Created using spr 1.3.4 --- bolt/lib/Pro

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt]; //===--===// let Predicates = [HasStdExtQ] in { - let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in - def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$r

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Add helpers for Template config (PR #138062)

https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138062 >From 4e26ed5b43593bdc7dbac86557e9ff2ba0c85fa7 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Wed, 30 Apr 2025 08:10:20 -0700 Subject: [PATCH] [clang-doc] Add helpers for Template config This patch adds or fil

[llvm-branch-commits] [clang-tools-extra] [clang-doc] Extract Info into JSON values (PR #138063)

https://github.com/ilovepi updated https://github.com/llvm/llvm-project/pull/138063 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-s

[llvm-branch-commits] [clang] [Clang][Backport] Fix handling of reference types in tryEvaluateBuiltinObjectSize (#138247) (PR #139579)

llvmbot wrote: @llvm/pr-subscribers-clang Author: cor3ntin (cor3ntin) Changes The order of operation was slightly incorrect, as we were checking for incomplete types *before* handling reference types. Fixes #129397 - --- Full diff: https://github.com/llvm/llvm-project/pull/1395

[llvm-branch-commits] [llvm] AMDGPU: Disable most fmed3 folds for strictfp (PR #139530)

https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/139530 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [Clang][Backport] Fix handling of reference types in tryEvaluateBuiltinObjectSize (#138247) (PR #139579)

https://github.com/erichkeane approved this pull request. https://github.com/llvm/llvm-project/pull/139579 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Use minnum instead of maxnum for fmed3 src2-nan fold (PR #139531)

https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/139531 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [analyzer] Workaround for slowdown spikes (unintended scope increase) (#136720) (PR #139597)

steakhal wrote: This is a manual backport of #136720. https://github.com/llvm/llvm-project/pull/139597 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] AArch64: Relax x16/x17 constraint on AUT in certain cases. (PR #132857)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/132857 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] Extract SipHash implementation into a header. (PR #134197)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/134197 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] [lld] ELF: Introduce R_AARCH64_FUNCINIT64 relocation type. (PR #133531)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133531 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] [compiler-rt] compiler-rt: Introduce runtime functions for emulated PAC. (PR #133530)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133530 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] [compiler-rt] compiler-rt: Introduce runtime functions for emulated PAC. (PR #133530)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133530 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] ELF: Add a -z glibc-228-compat flag for working around an old glibc bug. (PR #133532)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133532 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] Extract SipHash implementation into a header. (PR #134197)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/134197 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] AArch64: Relax x16/x17 constraint on AUT in certain cases. (PR #132857)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/132857 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] ELF: Introduce R_AARCH64_FUNCINIT64 relocation type. (PR #133531)

https://github.com/pcc edited https://github.com/llvm/llvm-project/pull/133531 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] ELF: Add a -z glibc-228-compat flag for working around an old glibc bug. (PR #133532)

https://github.com/pcc edited https://github.com/llvm/llvm-project/pull/133532 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] ELF: Introduce R_AARCH64_FUNCINIT64 relocation type. (PR #133531)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133531 >From 96e7da9a083888683c2ba00d97f886fd748ea10b Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Wed, 9 Apr 2025 20:30:57 -0700 Subject: [PATCH] Undo unnecessary change Created using spr 1.3.6-beta.1 --- lld

[llvm-branch-commits] Add IR and codegen support for deactivation symbols. (PR #133536)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133536 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] MachineInstrBuilder: Introduce copyMIMetadata() function. (PR #133535)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133535 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] ELF: Add support for R_AARCH64_INST32 relocation. (PR #133534)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133534 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] CodeGen: Optionally emit PAuth relocations as IRELATIVE relocations. (PR #133533)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133533 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] CodeGen: Optionally emit PAuth relocations as IRELATIVE relocations. (PR #133533)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133533 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] Add IR and codegen support for deactivation symbols. (PR #133536)

https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133536 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-serif,

[llvm-branch-commits] ELF: Add support for R_AARCH64_INST32 relocation. (PR #133534)

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[llvm-branch-commits] Add deactivation symbol operand to ConstantPtrAuth. (PR #133537)

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[llvm-branch-commits] Add pointer field protection feature. (PR #133538)

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[llvm-branch-commits] Add pointer field protection feature. (PR #133538)

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[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139508 >From 1a1cb30959da66d02bf64927ca7fcc5f8de290dc Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 15:04:28 +0800 Subject: [PATCH] [RISCV][MC] Add Q support for Zfa --- llvm/lib/Target/RI

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139508 >From 1a1cb30959da66d02bf64927ca7fcc5f8de290dc Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 15:04:28 +0800 Subject: [PATCH] [RISCV][MC] Add Q support for Zfa --- llvm/lib/Target/RI

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139495 >From 4fe33b2443138357709c890023abc8ba4d974ab7 Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 13:32:41 +0800 Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q ex

[llvm-branch-commits] [lld] ELF: Introduce R_AARCH64_FUNCINIT64 relocation type. (PR #133531)

pcc wrote: I've now implemented the ADDRINIT64 (renamed FUNCINIT64, but no strong opinions on the name) proposal as well as filed an issue with the AArch64 psABI: https://github.com/ARM-software/abi-aa/issues/329 https://github.com/llvm/llvm-project/pull/133531

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139495 >From a3dd59810a7b20bfc941d5723b8f4e9a1619234a Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 13:32:41 +0800 Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q ex

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139508 >From e8c188a0ea28030c01af913f9cc4eb57e9224a9c Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 15:04:28 +0800 Subject: [PATCH] [RISCV][MC] Add Q support for Zfa --- llvm/lib/Target/RI

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139495 >From a3dd59810a7b20bfc941d5723b8f4e9a1619234a Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 13:32:41 +0800 Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q ex

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139508 >From e8c188a0ea28030c01af913f9cc4eb57e9224a9c Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 15:04:28 +0800 Subject: [PATCH] [RISCV][MC] Add Q support for Zfa --- llvm/lib/Target/RI

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

https://github.com/el-ev updated https://github.com/llvm/llvm-project/pull/139495 >From 4fe33b2443138357709c890023abc8ba4d974ab7 Mon Sep 17 00:00:00 2001 From: Iris Shi <0...@owo.li> Date: Mon, 12 May 2025 13:32:41 +0800 Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q ex

[llvm-branch-commits] [BOLT] Drop perf2bolt cold samples diagnostic (PR #139337)

https://github.com/maksfb approved this pull request. https://github.com/llvm/llvm-project/pull/139337 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [BOLT] Print heatmap from perf2bolt (PR #139194)

https://github.com/maksfb approved this pull request. https://github.com/llvm/llvm-project/pull/139194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] release/20.x: [AArch64] Fix feature list for FUJITSU-MONAKA processor (#139212) (PR #139222)

ytmukai wrote: Thank you for the review! https://github.com/llvm/llvm-project/pull/139222 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [GlobalISel] Add computeNumSignBits for G_SHUFFLE_VECTOR (PR #139505)

@@ -874,6 +874,30 @@ unsigned GISelValueTracking::computeNumSignBits(Register R, SrcTy.getScalarSizeInBits()); break; } + case TargetOpcode::G_SHUFFLE_VECTOR: { +// Collect the minimum number of sign bits that are shared by ever

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Complete optimized regalloc pipeline (PR #138491)

@@ -2174,7 +2174,44 @@ void AMDGPUCodeGenPassBuilder::addMachineSSAOptimization( addPass(SIShrinkInstructionsPass()); } +void AMDGPUCodeGenPassBuilder::addOptimizedRegAlloc( +AddMachinePass &addPass) const { + if (EnableDCEInRA) +insertPass(DeadMachineInstructionEli

[llvm-branch-commits] [llvm] [GlobalISel] Add computeKnownBits for G_SHUFFLE_VECTOR (PR #139505)

@@ -400,9 +400,10 @@ define <8 x i16> @missing_insert(<8 x i8> %b) { ; ; CHECK-GI-LABEL: missing_insert: ; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT:sshll v0.8h, v0.8b, #0 -; CHECK-GI-NEXT:ext v1.16b, v0.16b, v0.16b, #4 -; CHECK-GI-NEXT:mul v0.8h, v1.8h,

[llvm-branch-commits] [llvm] AMDGPU: Add fmed3 fold tests with flags (PR #139546)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/139546 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] AMDGPU: Add fmed3 fold tests with flags (PR #139546)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/139546 AMDGPU: Add fmed3 fold tests with flags AMDGPU: Use minimumnum/maximumnum for fmed3 with amdgpu-ieee=0 Try to respect the signaling nan behavior of the instruction, so also start the special case fold for src2.

[llvm-branch-commits] [llvm] AMDGPU: Add fmed3 fold tests with flags (PR #139546)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/139546?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] [GlobalISel] Add computeNumSignBits for G_SHUFFLE_VECTOR (PR #139505)

https://github.com/jayfoad edited https://github.com/llvm/llvm-project/pull/139505 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [GlobalISel] Add computeNumSignBits for G_SHUFFLE_VECTOR (PR #139505)

@@ -874,6 +874,30 @@ unsigned GISelValueTracking::computeNumSignBits(Register R, SrcTy.getScalarSizeInBits()); break; } + case TargetOpcode::G_SHUFFLE_VECTOR: { +// Collect the minimum number of sign bits that are shared by ever

[llvm-branch-commits] [llvm] [LoopInterchange] Relax the legality check to accept more patterns (PR #118267)

https://github.com/Meinersbur approved this pull request. LGTM, thank you. https://github.com/llvm/llvm-project/pull/118267 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bra

[llvm-branch-commits] [llvm] release/20.x: [X86][TargetLowering] Avoid deleting temporary nodes in `getNegatedExpression` (#139029) (PR #139356)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/139356 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [LoopInterchange] Relax the legality check to accept more patterns (PR #118267)

kasuga-fj wrote: Thanks for your review. https://github.com/llvm/llvm-project/pull/118267 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [ObjC] Support objc_claimAutoreleasedReturnValue (PR #138696)

https://github.com/citymarina updated https://github.com/llvm/llvm-project/pull/138696 >From e83258e216f89992a7c46eaf3478c7b31e1113dc Mon Sep 17 00:00:00 2001 From: Marina Taylor Date: Wed, 19 Mar 2025 18:25:09 + Subject: [PATCH] [ObjC] Support objc_claimAutoreleasedReturnValue. This adds

[llvm-branch-commits] [llvm] [ObjC] Support objc_claimAutoreleasedReturnValue (PR #138696)

@@ -9545,7 +9545,9 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, // Do what the frontend tells us: if the rvmarker module flag is present, // emit the marker. Always emit the call regardless. // Tell the pseudo expansion using an additional boolean op.

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