https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/137703
Codegen for AArch64 16/32/64-bit floating-point atomic read-modify-write
operations (`atomicrmw {fmaximum,fminimum}`) using LD{B}FMAX and LD{B}FMIN
atomic instructions.
>From 6152e58a72cdd9f398250d4320dc513c
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/137702
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llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Jonathan Thackray (jthackray)
Changes
Codegen for AArch64 16/32/64-bit floating-point atomic read-modify-write
operations (`atomicrmw {fmaximum,fminimum}`) using LD{B}FMAX and LD{B}FMIN
atomic instructions.
---
Patch is 71.76
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/137707
Backport 59978b21ad9c65276ee8e14f26759691b8a65763
Requested by: @tstellar
>From 29b693e7af536fcd200e0b68db01ab29a46b11a3 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Mon, 28 Apr 2025 13:45:11 -0700
Subjec
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/137707
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llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: None (llvmbot)
Changes
Backport 59978b21ad9c65276ee8e14f26759691b8a65763
Requested by: @tstellar
---
Full diff: https://github.com/llvm/llvm-project/pull/137707.diff
3 Files Affected:
- (modified)
compiler-rt/lib/sanit
llvmbot wrote:
@enh-google What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/137707
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@@ -1421,6 +1424,35 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N,
unsigned ResNo) {
SetSplitVector(SDValue(N, ResNo), Lo, Hi);
}
+void DAGTypeLegalizer::SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD) {
jofrn wrote:
I had tried doing it by splitting L
https://github.com/kasuga-fj created
https://github.com/llvm/llvm-project/pull/137663
In MachinePipeliner, loop-carried memory dependencies are represented by DAG,
which makes things complicated and causes some necessary dependencies to be
missing. This patch introduces a new class to manage l
@@ -1421,6 +1424,35 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N,
unsigned ResNo) {
SetSplitVector(SDValue(N, ResNo), Lo, Hi);
}
+void DAGTypeLegalizer::SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD) {
+ SDLoc dl(LD);
+
+ EVT MemoryVT = LD->getMemoryVT();
+ unsigne
llvmbot wrote:
@llvm/pr-subscribers-backend-hexagon
Author: Ryotaro Kasuga (kasuga-fj)
Changes
In MachinePipeliner, loop-carried memory dependencies are represented by DAG,
which makes things complicated and causes some necessary dependencies to be
missing. This patch introduces a new cl
tblah wrote:
The new testsuite failures look unrelated to my patch
https://github.com/llvm/llvm-project/pull/137205
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