mtrofin wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131417?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/127432
>From 7e29d6ace39058b631dcfff5533d8aee055de6dd Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Mon, 3 Mar 2025 12:25:13 +0900
Subject: [PATCH 1/3] obj2yaml
---
llvm/include/llvm/ObjectYAML/CovMap.h
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/127432
>From 7e29d6ace39058b631dcfff5533d8aee055de6dd Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Mon, 3 Mar 2025 12:25:13 +0900
Subject: [PATCH 1/3] obj2yaml
---
llvm/include/llvm/ObjectYAML/CovMap.h
https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/129473
>From e2dd98690a0f43b35ee22d59efeb04d2c7fead68 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Mon, 3 Mar 2025 12:26:08 +0900
Subject: [PATCH] detailed
---
llvm/include/llvm/ObjectYAML/CovMap.h | 9
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/131417
>From 5916e7d345d84368b18cc08e32e2c63e4b967ec3 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Fri, 14 Mar 2025 15:59:22 -0700
Subject: [PATCH] [ctxprof] Track unhandled call targets
---
.../lib/ctx_profile
https://github.com/clementval edited
https://github.com/llvm/llvm-project/pull/131399
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@@ -258,6 +258,14 @@ def sext_trunc_sextload : GICombineRule<
[{ return Helper.matchSextTruncSextLoad(*${d}); }]),
(apply [{ Helper.applySextTruncSextLoad(*${d}); }])>;
+def sext_trunc_sextinreg : GICombineRule<
+ (defs root:$dst),
+ (match (G_SEXT_INREG $sir, $sr
https://github.com/yonghong-song updated
https://github.com/llvm/llvm-project/pull/130995
>From 9d7369b1c4f1b40d5e3a2e69616f79aad3a5 Mon Sep 17 00:00:00 2001
From: yonghong-song
Date: Tue, 11 Mar 2025 11:23:53 -0700
Subject: [PATCH] [BPF] Fix BitCast Assertion with NonZero AddrSpace
Alexei
https://github.com/mtrofin created
https://github.com/llvm/llvm-project/pull/131417
None
>From 95e5589a1520e3ab1fb1c74262bc03b430d14ee1 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Fri, 14 Mar 2025 15:59:22 -0700
Subject: [PATCH] [ctxprof] Track unhandled call targets
---
.../lib/ctx_p
mtrofin wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131416?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/131417
>From 9f54f192becbe116784aec08d60d7c849f559b88 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Fri, 14 Mar 2025 15:59:22 -0700
Subject: [PATCH] [ctxprof] Track unhandled call targets
---
.../lib/ctx_profile
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131317?utm_source=stack-comment-downstack-mergeability-warning";
@@ -1278,7 +1278,11 @@ bool AMDGPUCallLowering::lowerTailCall(
if (auto CI = dyn_cast(Arg.OrigValue)) {
MIB.addImm(CI->getSExtValue());
} else {
-MIB.addReg(Arg.Regs[0]);
+Register Reg = Arg.Regs[0];
+if (!MRI.getVRegDef(Reg)->isCopy(
arsenm wrote:
> SI_CS_CHAIN adds register classes to generic instruction. This causes
> legalize combiner to break.
Break how? This should still work
https://github.com/llvm/llvm-project/pull/131329
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@@ -0,0 +1,11 @@
+; RUN: not --crash llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 -global-isel=1
-mattr=+wavefrontsize64 -verify-machineinstrs=0 < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 -global-isel=0
-mattr=+wavefrontsize64 -verify-machineinst
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/131317
>From 0bccd4581d72280722f34f28e87682dd27e59c5c Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 14 Mar 2025 18:06:43 +0700
Subject: [PATCH] AMDGPU: Switch simplifydemandedbits-recursion.ll to generated
c
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/131315
>From 1b2648aa5b6f91032e35d53888fa521046c385fd Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 14 Mar 2025 17:04:33 +0700
Subject: [PATCH] AMDGPU: Switch test to generated checks
I doubt this is testing
@@ -1200,34 +1225,79 @@ bool AMDGPUCallLowering::lowerTailCall(
if (!IsSibCall)
CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
- unsigned Opc =
- getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC);
+ bool IsChainCall = AMDGPU::isC
https://github.com/mihajlovicana created
https://github.com/llvm/llvm-project/pull/131329
SI_CS_CHAIN adds register classes to generic instruction. This causes legalize
combiner to break.
Patch fixes this issue by adding COPY instructions.
>From 3e36fbad5d782690ef845f754f3203d9d79b0602 Mon Sep
arsenm wrote:
> GlobalISel unfortunately needs it. We can end up with things like a `G_LSHR`
> with the shift amount being zext'd, and they're both lowered independently so
> we have a `s_and_b32` of the shift amount.
It should always be post legalize / post regbankselect combinable. Things ar
@@ -1200,34 +1225,79 @@ bool AMDGPUCallLowering::lowerTailCall(
if (!IsSibCall)
CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
- unsigned Opc =
- getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC);
+ bool IsChainCall = AMDGPU::isC
arsenm wrote:
> Then %2 being used as the shift amount. We can't eliminate the zext/trunc
> because the generic opcode has no mention of reading only the lower bits,
> AFAIK.
We can fold the clamp of the shift amount into the shift instruction during
selection as we know the instruction ignor
https://github.com/artempyanykh updated
https://github.com/llvm/llvm-project/pull/129154
>From 57c903cb893cde348fe3ac2edc474a32af2120fa Mon Sep 17 00:00:00 2001
From: Artem Pianykh
Date: Tue, 25 Feb 2025 13:09:23 -0800
Subject: [PATCH] [NFC][Cloning] Move DebugInfoFinder decl closer to its plac
https://github.com/artempyanykh updated
https://github.com/llvm/llvm-project/pull/129152
>From 6b37028d86e1ebd8a4069bfa07fd657108398954 Mon Sep 17 00:00:00 2001
From: Artem Pianykh
Date: Tue, 25 Feb 2025 13:02:37 -0800
Subject: [PATCH] [NFC][Cloning] Remove now unused CollectDebugInfoForCloning
https://github.com/artempyanykh updated
https://github.com/llvm/llvm-project/pull/129153
>From cd22b5339a222d63c320b91d92f83b18f43e00c6 Mon Sep 17 00:00:00 2001
From: Artem Pianykh
Date: Tue, 25 Feb 2025 13:07:40 -0800
Subject: [PATCH] [NFC][Cloning] Clean up comments in CloneFunctionInto
Summ
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/131382
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https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/129762
>From 03fdc56648c828794749d6d9e8a7a0d28e26a4c6 Mon Sep 17 00:00:00 2001
From: Nick Fitzgerald
Date: Tue, 4 Mar 2025 09:39:30 -0800
Subject: [PATCH] [lld][WebAssembly] Support for the custom-page-sizes
WebAssemb
https://github.com/hekota created
https://github.com/llvm/llvm-project/pull/131384
Updates the `BuiltinTypeMethodBuilder` to support creating constructors and use
it to create the default resource constructor. This enables us to have a shared
code for implementing both builtin methods and cons
https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/131384
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https://github.com/artempyanykh updated
https://github.com/llvm/llvm-project/pull/129154
>From cf575ea42b6722ad90131bbb45f1104225a9f75d Mon Sep 17 00:00:00 2001
From: Artem Pianykh
Date: Tue, 25 Feb 2025 13:09:23 -0800
Subject: [PATCH] [NFC][Cloning] Move DebugInfoFinder decl closer to its plac
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131309
Make s16 G_U/SBFX legal and widen them in RegBankSelect.
This allows the set of BFX formation combines to work on s16 types.
>From ee917df6c6e996135d1b08f924b6645649eafa0d Mon Sep 17 00:00:00 2001
From: pvanho
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/131308
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-llvm-globalisel
Author: Pierre van Houtryve (Pierre-vh)
Changes
Make s16 G_U/SBFX legal and widen them in RegBankSelect.
This allows the set of BFX formation combines to work on s16 types.
---
Patch is 95.48 KiB, tru
https://github.com/clementval created
https://github.com/llvm/llvm-project/pull/131395
Add a pass to compute the size of the shared memory (static shared memory) and
the offsets of each variables to be placed in shared memory. The global
representing the shared memory is also created during th
llvmbot wrote:
@llvm/pr-subscribers-flang-fir-hlfir
Author: Valentin Clement (バレンタイン クレメン) (clementval)
Changes
Add a pass to compute the size of the shared memory (static shared memory) and
the offsets of each variables to be placed in shared memory. The global
representing the shared m
https://github.com/clementval created
https://github.com/llvm/llvm-project/pull/131396
Convert the operation to `llvm.addressof` operation with `llvm.getelementptr`
with the appropriate offset.
>From bd44073dc01ff6b5dce02490eeceb8a52f2130b4 Mon Sep 17 00:00:00 2001
From: Valentin Clement
Dat
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/131398
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llvmbot wrote:
@llvm/pr-subscribers-llvm-binary-utilities
Author: None (llvmbot)
Changes
Backport 8413f4d837a96458104f63bab72c751b8285a458
Requested by: @nikic
---
Full diff: https://github.com/llvm/llvm-project/pull/131398.diff
2 Files Affected:
- (modified) llvm/lib/ObjCopy/MachO/Ma
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/131398
Backport 8413f4d837a96458104f63bab72c751b8285a458
Requested by: @nikic
>From cb50aaf8a11b89f2785641fba5ffd4b67f566a32 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Daniel=20Rodr=C3=ADguez=20Troiti=C3=B1o?=
Date: F
llvmbot wrote:
@drodriguez What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/131398
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https://github.com/clementval created
https://github.com/llvm/llvm-project/pull/131399
None
>From 2dc9b157230a7e9b64fa1af7b2a30faaf8af2da9 Mon Sep 17 00:00:00 2001
From: Valentin Clement
Date: Fri, 14 Mar 2025 14:47:31 -0700
Subject: [PATCH] [flang][cuda] Lower CUDA shared variable with
cuf.s
https://github.com/drodriguez approved this pull request.
https://github.com/llvm/llvm-project/pull/131398
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llvmbot wrote:
@llvm/pr-subscribers-flang-fir-hlfir
Author: Valentin Clement (バレンタイン クレメン) (clementval)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/131399.diff
2 Files Affected:
- (modified) flang/lib/Lower/ConvertVariable.cpp (+10-4)
- (added) flang/test/Lower/C
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/131259
>From 1907a9f5941abc6938e8a597a4b3da0f4eb2bcd2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 14 Mar 2025 09:14:10 +0700
Subject: [PATCH] AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll
tes
arsenm wrote:
### Merge activity
* **Mar 14, 3:38 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/131256).
https://github.com/llvm/llvm-project/pull/131256
_
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/131382
Backport 672e385
Requested by: @ian-twilightcoder
>From 5c899c9694bf13e48f5959feb4189540f56328b9 Mon Sep 17 00:00:00 2001
From: Takuto Ikuta
Date: Thu, 13 Feb 2025 16:54:43 +0900
Subject: [PATCH] [libcxx] Add
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87574
>From 1d7ee612e408ee7e64e984eb08e6d7089a435d09 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Sun, 2 Feb 2025 00:58:49 +
Subject: [PATCH 1/4] Simplify MIR test.
Created using spr 1.3.6-beta.1
---
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87575
>From 1a8d810d352fbe84c0521c7614689b60ade693c8 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Tue, 19 Nov 2024 15:25:34 -0800
Subject: [PATCH 1/4] Fixed the tests and addressed most of the review
comm
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87576
>From 6b67376bd5e1f21606017c83cc67f2186ba36a33 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Thu, 13 Mar 2025 01:41:04 +
Subject: [PATCH 1/4] Updated the test as reviewers suggested.
Created usin
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87576
>From 6b67376bd5e1f21606017c83cc67f2186ba36a33 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Thu, 13 Mar 2025 01:41:04 +
Subject: [PATCH 1/4] Updated the test as reviewers suggested.
Created usin
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/117036
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https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/117037
>From 6a12be2c5b60a95a06875b0b2c4f14228d1fa882 Mon Sep 17 00:00:00 2001
From: prabhukr
Date: Wed, 12 Mar 2025 23:30:01 +
Subject: [PATCH] Fix EOF newlines.
Created using spr 1.3.6-beta.1
---
clang/test/Dri
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/117036
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Prabhuk wrote:
@nikic -- ping
https://github.com/llvm/llvm-project/pull/87573
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/131315
I doubt this is testing what it originally intended anymore. Also
replace an undef.
>From 22bcd308bc6c862859281bdcab9361a905fa3d54 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 14 Mar 2025 17:04:33 +0
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/131315
>From 7b23925faefc723e69bb5afc04a5b2c47fca178b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 14 Mar 2025 17:04:33 +0700
Subject: [PATCH] AMDGPU: Switch test to generated checks
I doubt this is testing
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/131316
>From 69d40c9315c409efdd612fc4f4f97663107918ef Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 14 Mar 2025 18:03:12 +0700
Subject: [PATCH] AMDGPU: Switch scheduler-subrange-crash.ll to generated
checks
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/131317
>From c64c89f8277ed1bcbd0e5fa9f889d31b67f12003 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 14 Mar 2025 18:06:43 +0700
Subject: [PATCH] AMDGPU: Switch simplifydemandedbits-recursion.ll to generated
c
@@ -0,0 +1,47 @@
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apac
mizvekov wrote:
It complains about missing third-party header "fmt/format.h".
Even after figuring out what that is and installing it, I can't get your
project to build on a known-good compiler.
I am not asking for a reduced reproducer, just a preprocessed one. You can do
that by appending "-ge
https://github.com/artempyanykh updated
https://github.com/llvm/llvm-project/pull/129152
>From 712ba5da1e8d68be2d2b4086e35f447828938d55 Mon Sep 17 00:00:00 2001
From: Artem Pianykh
Date: Tue, 25 Feb 2025 13:02:37 -0800
Subject: [PATCH] [NFC][Cloning] Remove now unused CollectDebugInfoForCloning
llvmbot wrote:
@philnik777 What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/131382
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https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/131384
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https://github.com/artempyanykh updated
https://github.com/llvm/llvm-project/pull/129153
>From 3779d77170ceb62f7b896670cd86f1dca7469085 Mon Sep 17 00:00:00 2001
From: Artem Pianykh
Date: Tue, 25 Feb 2025 13:07:40 -0800
Subject: [PATCH] [NFC][Cloning] Clean up comments in CloneFunctionInto
Summ
https://github.com/wangzpgi approved this pull request.
https://github.com/llvm/llvm-project/pull/131396
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https://github.com/wangzpgi approved this pull request.
https://github.com/llvm/llvm-project/pull/131399
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@@ -0,0 +1,126 @@
+//===-- CUFComputeSharedMemoryOffsetsAndSize.cpp
--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
drodriguez wrote:
> @drodriguez What do you think about merging this PR to the release branch?
@nikic I imagine this is you asking and not a sentient robot? :D
I think the fix is safe enough for cherry-picking into the release branch. A
couple of people in the issue, PR, and related issues I h
https://github.com/wangzpgi approved this pull request.
https://github.com/llvm/llvm-project/pull/131395
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Valentin Clement =?utf-8?b?KOODkOODrOODsw=?Message-ID:
In-Reply-To:
https://github.com/clementval updated
https://github.com/llvm/llvm-project/pull/131395
>From bd481839b595df26ec54ecf75ecdedef5425c0dd Mon Sep 17 00:00:00 2001
From: Valentin Clement
Date: Fri, 14 Mar 2025 14:19:08 -0700
Subje
@@ -0,0 +1,126 @@
+//===-- CUFComputeSharedMemoryOffsetsAndSize.cpp
--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
TimNN wrote:
> but not the dynamic loaded itself in my experience
We actually found this because the resulting binaries fail to launch on iOS:
https://github.com/rust-lang/rust/issues/138212
https://github.com/llvm/llvm-project/pull/131398
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drodriguez wrote:
That's why I added "in my experience". I never got a failing binary, but
there's yours and another report in the original PR. I never got a failing
binary, but I cannot give you a reason why. The `dyld_info` analysis is pretty
clear, but it is sometimes more strict than `dyld
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131288?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/130617
>From 0e11e500920a20bee3c354d9474e91995081f7ab Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Mon, 10 Mar 2025 06:55:10 -0400
Subject: [PATCH 1/2] [SeparateConstOffsetFromGEP] Preserve inbounds flag based
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/131275
>From 54435ee128658dee69573144a830e4cdb48ba630 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 14 Mar 2025 09:27:07 +0700
Subject: [PATCH] AMDGPU: Use generated checks in unchecked test
Also replace und
arsenm wrote:
### Merge activity
* **Mar 14, 3:38 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/131255).
https://github.com/llvm/llvm-project/pull/131255
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jayfoad wrote:
Same kind of objection as #131287: as a general strategy, "replace unused
inputs with poison" seems incompatible with "propagate poison from arguments to
result". @nunoplopes any thoughts on this?
https://github.com/llvm/llvm-project/pull/131288
_
arsenm wrote:
> I have a conceptual objection: I don't think we can do both of these things:
>
> 1. Replace unused inputs of all intrinsics with poison
> 2. Propagate poison from any argument, for all intrinsics
>
> So how should we handle this in general? Is it better to replace unused
> inpu
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131312
This is a bit of an akward pattern that can come up as a result
of legalization and then widening of i16 operations to i32 in RegBankSelect
on AMDGPU.
This quick combine avoids redundant patterns like
```
s_se
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131308
It's better to widen them to avoid it being lowered into a G_ASHR + G_SHL. With
this change we just extend to i32 then trunc the result.
>From 815595b1ca20b613b5b4b08cafedda93e397cf92 Mon Sep 17 00:00:00 2001
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131310
None
>From b87a9db3b8ab29db3f1bb668a4d3bf312add817b Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:00:21 +0100
Subject: [PATCH] [AMDGPU] Precommit si-fold-bitmask.mir
---
llvm/test/CodeGe
nunoplopes wrote:
We don't propagate poison through intrinsics blindly. We do it when the
semantics allow it.
Using poison as placeholder for unused lanes, don't care bits, etc is fine. But
you are right that then we cannot make the intrinsic return poison because
those arguments are poison.
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131307?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131311
Instructions like shifts only read some of the bits of the shift amount
operand, between 4 and 6 bits.
If the source operand is being masked, we can just ignore the mask.
Effects are minimal right now but thi
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131306?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/131310
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https://github.com/jayfoad approved this pull request.
https://github.com/llvm/llvm-project/pull/131286
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jayfoad wrote:
I have a conceptual objection: I don't think we can do both of these things:
1. Replace unused inputs of all intrinsics with poison
2. Propagate poison from any argument, for all intrinsics
So how should we handle this in general? Is it better to replace unused inputs
with "free
arsenm wrote:
### Merge activity
* **Mar 14, 7:10 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/131276).
https://github.com/llvm/llvm-project/pull/131276
_
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
Author: Pierre van Houtryve (Pierre-vh)
Changes
Instructions like shifts only read some of the bits of the shift amount
operand, between 4 and 6 bits.
If the source operand is being masked, we can just ignore the mask.
Effects are minim
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
@llvm/pr-subscribers-backend-amdgpu
Author: Pierre van Houtryve (Pierre-vh)
Changes
It's better to widen them to avoid it being lowered into a G_ASHR + G_SHL. With
this change we just extend to i32 then trunc the result.
---
Patch is 6
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff b87a9db3b8ab29db3f1bb668a4d3bf312add817b
f46e24f0f5f98e5deb7bd13d737ed8c674da75e1 --e
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff ee03ddb50d99b34981cf2cde9049829ff89a9035
815595b1ca20b613b5b4b08cafedda93e397cf92 --e
jayfoad wrote:
> We do it when the semantics allow it.
My concern is that it is not obvious when the semantics allow it, when you have
a plethora of undocumented target intrinsics. I guess the grown-up solution is
to document them properly.
https://github.com/llvm/llvm-project/pull/131287
___
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131312
>From b9bf3f2f53fcf7cbd133e57d4c7f64a8f06763b2 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:34:51 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Combine (sext (trunc (sext_in_reg x)))
This i
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131306
>From 1af83464f02df212384bd97848b0073d41053234 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 5 Mar 2025 10:46:01 +0100
Subject: [PATCH] [AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32
See #645
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