@@ -306,4 +307,254 @@ TEST_F(ParseHLSLRootSignatureTest,
InvalidLexRegNumberTest) {
ASSERT_FALSE(Consumer->IsSatisfied());
}
+// Valid Parser Tests
+
+TEST_F(ParseHLSLRootSignatureTest, ValidParseEmptyTest) {
+ const llvm::StringLiteral Source = R"cc()cc";
+
+ TrivialModu
@@ -93,6 +96,108 @@ class RootSignatureLexer {
}
};
+class RootSignatureParser {
+public:
+ RootSignatureParser(SmallVector &Elements,
+ RootSignatureLexer &Lexer, DiagnosticsEngine &Diags);
+
+ /// Iterates over the provided tokens and constructs the
@@ -93,6 +96,108 @@ class RootSignatureLexer {
}
};
+class RootSignatureParser {
+public:
+ RootSignatureParser(SmallVector &Elements,
+ RootSignatureLexer &Lexer, DiagnosticsEngine &Diags);
+
+ /// Iterates over the provided tokens and constructs the
@@ -93,6 +96,108 @@ class RootSignatureLexer {
}
};
+class RootSignatureParser {
+public:
+ RootSignatureParser(SmallVector &Elements,
+ RootSignatureLexer &Lexer, DiagnosticsEngine &Diags);
+
+ /// Iterates over the provided tokens and constructs the
@@ -93,6 +96,108 @@ class RootSignatureLexer {
}
};
+class RootSignatureParser {
+public:
+ RootSignatureParser(SmallVector &Elements,
+ RootSignatureLexer &Lexer, DiagnosticsEngine &Diags);
+
+ /// Iterates over the provided tokens and constructs the
@@ -1,8 +1,65 @@
#include "clang/Parse/ParseHLSLRootSignature.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm::hlsl::rootsig;
+
namespace clang {
namespace hlsl {
+// Helper definitions
bogner wrote:
This comment isn't very helpful.
http
@@ -162,5 +219,371 @@ std::optional
RootSignatureLexer::PeekNextToken() {
return Result;
}
+// Parser Definitions
+
+RootSignatureParser::RootSignatureParser(SmallVector &Elements,
+ RootSignatureLexer &Lexer,
+
@@ -162,5 +219,371 @@ std::optional
RootSignatureLexer::PeekNextToken() {
return Result;
}
+// Parser Definitions
+
+RootSignatureParser::RootSignatureParser(SmallVector &Elements,
+ RootSignatureLexer &Lexer,
+
@@ -162,5 +219,371 @@ std::optional
RootSignatureLexer::PeekNextToken() {
return Result;
}
+// Parser Definitions
+
+RootSignatureParser::RootSignatureParser(SmallVector &Elements,
+ RootSignatureLexer &Lexer,
+
@@ -93,6 +96,108 @@ class RootSignatureLexer {
}
};
+class RootSignatureParser {
+public:
+ RootSignatureParser(SmallVector &Elements,
+ RootSignatureLexer &Lexer, DiagnosticsEngine &Diags);
+
+ /// Iterates over the provided tokens and constructs the
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/126843
>From a7f00c8ed8c20a006fd7e592e99f3ca7b725b07e Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Thu, 30 Jan 2025 18:03:04 -0800
Subject: [PATCH] [clang-format] Fix a crash on parsing requires clause
(#125021)
Fix
Author: Owen Pan
Date: 2025-02-13T18:38:24-08:00
New Revision: a7f00c8ed8c20a006fd7e592e99f3ca7b725b07e
URL:
https://github.com/llvm/llvm-project/commit/a7f00c8ed8c20a006fd7e592e99f3ca7b725b07e
DIFF:
https://github.com/llvm/llvm-project/commit/a7f00c8ed8c20a006fd7e592e99f3ca7b725b07e.diff
LOG:
github-actions[bot] wrote:
@owenca (or anyone else). If you would like to add a note about this fix in the
release notes (completely optional). Please reply to this comment with a one or
two sentence description of the fix. When you are done, please add the
release:note label to this PR.
ht
https://github.com/tstellar closed
https://github.com/llvm/llvm-project/pull/126843
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/118462
>From ed461217c0323fa1d172b42e81e20900653758c9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 3 Dec 2024 10:12:36 +
Subject: [PATCH 1/9] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to
NPM
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From b407c8640b5936bcd6824bd0ab550243ae6a7f3b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 08:51:55 +
Subject: [PATCH 1/7] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/120557
>From 6b013984ddb49a7c60a6eb60db33aa73f9e55c4d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 11 Feb 2025 12:36:40 +
Subject: [PATCH 1/2] [CodeGen][NewPM] Plug greedy RA in codegen pipeline
---
llv
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From b407c8640b5936bcd6824bd0ab550243ae6a7f3b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 08:51:55 +
Subject: [PATCH 1/7] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/125351
>From 4bf4fe28a25a1ac7e216b4dcd66da210114a5482 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Sat, 1 Feb 2025 18:21:24 +
Subject: [PATCH 1/2] [AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM
---
l
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/120557
>From 6b013984ddb49a7c60a6eb60db33aa73f9e55c4d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 11 Feb 2025 12:36:40 +
Subject: [PATCH 1/2] [CodeGen][NewPM] Plug greedy RA in codegen pipeline
---
llv
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/125351
>From 4bf4fe28a25a1ac7e216b4dcd66da210114a5482 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Sat, 1 Feb 2025 18:21:24 +
Subject: [PATCH 1/2] [AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM
---
l
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/118462
>From ed461217c0323fa1d172b42e81e20900653758c9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 3 Dec 2024 10:12:36 +
Subject: [PATCH 1/9] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to
NPM
https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/123600
>From 7993434e2973437b010034051003f8c03d8eff71 Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Fri, 27 Dec 2024 19:29:32 +0800
Subject: [PATCH 1/6] Relax TLS LE/GD/LD.
In local-exec form, the code sequence is co
https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/123576
>From f1f995b5fc8e90126b5825d52b9c75cd45d27cfc Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Thu, 26 Dec 2024 11:32:33 +0800
Subject: [PATCH 1/6] Relax call36/tail36.
Instructions with relocation `R_LARCH_CALL
https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/123600
>From 7993434e2973437b010034051003f8c03d8eff71 Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Fri, 27 Dec 2024 19:29:32 +0800
Subject: [PATCH 1/7] Relax TLS LE/GD/LD.
In local-exec form, the code sequence is co
https://github.com/qcolombet approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/127052
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https://github.com/hokein approved this pull request.
https://github.com/llvm/llvm-project/pull/127174
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@@ -1412,6 +1412,20 @@ parseBoundsCheckingOptions(StringRef Params) {
return Options;
}
+Expected
+parseRegAllocGreedyFilterFunc(PassBuilder &PB, StringRef Params) {
+ if (Params.empty() || Params == "all") {
+return RAGreedyPass::Options();
+ }
+ std::optional Filter
@@ -1412,6 +1412,20 @@ parseBoundsCheckingOptions(StringRef Params) {
return Options;
}
+Expected
+parseRegAllocGreedyFilterFunc(PassBuilder &PB, StringRef Params) {
+ if (Params.empty() || Params == "all") {
+return RAGreedyPass::Options();
+ }
cdevad
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/127051
Previously this would give up on folding subregister copies through
a reg_sequence if the input operand already had a subregister index.
d246cc618adc52fdbd69d44a2a375c8af97b6106 stopped introducing these
subregist
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/127051?utm_source=stack-comment-downstack-mergeability-warning";
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/127052?utm_source=stack-comment-downstack-mergeability-warning";
llvmbot wrote:
@llvm/pr-subscribers-llvm-regalloc
Author: Matt Arsenault (arsenm)
Changes
Previously this would give up on folding subregister copies through
a reg_sequence if the input operand already had a subregister index.
d246cc618adc52fdbd69d44a2a375c8af97b6106 stopped introducing th
llvmbot wrote:
@llvm/pr-subscribers-llvm-regalloc
@llvm/pr-subscribers-tablegen
Author: Matt Arsenault (arsenm)
Changes
This reverts d246cc618adc52fdbd69d44a2a375c8af97b6106. We now handle
composing subregister extracts through reg_sequence.
---
Patch is 576.74 KiB, truncated to 20.00 Ki
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/127052
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https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/127051
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https://github.com/Meinersbur updated
https://github.com/llvm/llvm-project/pull/124126
>From c515d13f0ad684763e6d76a87a610801482c15f4 Mon Sep 17 00:00:00 2001
From: Michael Kruse
Date: Fri, 24 Jan 2025 16:52:46 +0100
Subject: [PATCH 1/2] [Flang] Remove FLANG_INCLUDE_RUNTIME
---
flang/CMakeLis
https://github.com/Meinersbur updated
https://github.com/llvm/llvm-project/pull/121782
>From b05c9a033158aea459d51ff34b8ec47e72f85740 Mon Sep 17 00:00:00 2001
From: Michael Kruse
Date: Fri, 24 Jan 2025 16:51:27 +0100
Subject: [PATCH 1/2] [Flang-RT] Build libflang_rt.so
---
flang-rt/CMakeLists
@@ -248,7 +237,25 @@ else()
include_directories(SYSTEM ${MLIR_TABLEGEN_OUTPUT_DIR})
endif()
-option(FLANG_INCLUDE_RUNTIME "Build the runtime in-tree (deprecated; to be
replaced with LLVM_ENABLE_RUNTIMES=flang-rt)" ON)
+set(FLANG_INCLUDE_RUNTIME_default ON)
+if ("flang-rt" I
@@ -199,3 +201,28 @@ const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID
CC,
return MCConstantExpr::create(0, Ctx);
}
+
+uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF) {
+ if (!CodeSizeInBytes.has_value()) {
+const GCNSubtarget &STM = MF.ge
@@ -199,3 +201,28 @@ const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID
CC,
return MCConstantExpr::create(0, Ctx);
}
+
+uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF) {
+ if (!CodeSizeInBytes.has_value()) {
arsenm wrote:
shou
https://github.com/CarolineConcatto updated
https://github.com/llvm/llvm-project/pull/126513
>From b8f15433ed7ac0e63731cae7ab30672d5fe0703e Mon Sep 17 00:00:00 2001
From: CarolineConcatto
Date: Mon, 10 Feb 2025 13:14:13 +
Subject: [PATCH] Add release note for Armv9.6 updates
---
llvm/docs
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126906
>From 3be3e8dcc88ed73e52864e57e835d9cd9f31cdc7 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 08:04:43 -0500
Subject: [PATCH] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/125826
>From e8d38e53f175c5d481c6774b330f0da15d234322 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 5 Feb 2025 04:19:00 -0500
Subject: [PATCH] [AMDGPU] Replace gfx940 and gfx941 with gfx942 in offload and
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/125827
>From 55e82835c1fbf0259881c34dc55d7fd15cfd98a2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 5 Feb 2025 04:45:26 -0500
Subject: [PATCH] [AMDGPU] Add missing gfx architectures to
AddFlangOffloadRunt
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126762
>From 7398a7f3a441fca9fbcddcc2b5db1e6a57c52165 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 11 Feb 2025 08:52:55 -0500
Subject: [PATCH] [AMDGPU][clang] Replace gfx940 and gfx941 with gfx942 in
cla
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126887
>From 6bc2689cf31303be4451b7c8c79546465a1c1016 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 05:45:01 -0500
Subject: [PATCH] [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in
llvm
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/125836
>From d8557b87c87c4cf404f591e4f82e3c24928536fe Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 5 Feb 2025 05:50:12 -0500
Subject: [PATCH 1/2] [AMDGPU][MLIR] Replace gfx940 and gfx941 with gfx942 in
M
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126762
>From 7398a7f3a441fca9fbcddcc2b5db1e6a57c52165 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 11 Feb 2025 08:52:55 -0500
Subject: [PATCH] [AMDGPU][clang] Replace gfx940 and gfx941 with gfx942 in
cla
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126887
>From 6bc2689cf31303be4451b7c8c79546465a1c1016 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 05:45:01 -0500
Subject: [PATCH] [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in
llvm
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/125836
>From d8557b87c87c4cf404f591e4f82e3c24928536fe Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 5 Feb 2025 05:50:12 -0500
Subject: [PATCH 1/2] [AMDGPU][MLIR] Replace gfx940 and gfx941 with gfx942 in
M
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/125827
>From 55e82835c1fbf0259881c34dc55d7fd15cfd98a2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 5 Feb 2025 04:45:26 -0500
Subject: [PATCH] [AMDGPU] Add missing gfx architectures to
AddFlangOffloadRunt
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126878
>From baa8adda226fea78f2fd595edadf57af72d7d049 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 04:13:18 -0500
Subject: [PATCH] [AMDGPU] Remove FeatureForceStoreSC0SC1
This was only used f
@@ -199,3 +201,28 @@ const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID
CC,
return MCConstantExpr::create(0, Ctx);
}
+
+uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF) {
rampitec wrote:
I wanted to look at this separately. Righ
https://github.com/jeanPerier approved this pull request.
Thanks for addressing all my concerns! Let's roll!
https://github.com/llvm/llvm-project/pull/110217
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https://github.com/jeanPerier approved this pull request.
Thanks!
https://github.com/llvm/llvm-project/pull/121782
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https://github.com/jhuber6 approved this pull request.
https://github.com/llvm/llvm-project/pull/110217
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https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/125836
>From 411774e0d3d6007130fb16be18fe9a37da4e3bfe Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 5 Feb 2025 05:50:12 -0500
Subject: [PATCH 1/2] [AMDGPU][MLIR] Replace gfx940 and gfx941 with gfx942 in
M
Meinersbur wrote:
The pre-merge tests are failing. AFAICS, these are issues with the Buildkite
bots, not with this PR.
* buildkite/libcxx-ci/aarch64(-fno-exceptons): timeouts
* buildkite/github-pull-requests/linux-linux-x64 and /windows-windows-x64:
Linux reports failing to create the dire
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126762
>From a80db3a9fe9654bc91b9377f8d38e6270380f9a2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 11 Feb 2025 08:52:55 -0500
Subject: [PATCH] [AMDGPU][clang] Replace gfx940 and gfx941 with gfx942 in
cla
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126878
>From 731f633e66cf3118e5764ed4d0acbd794d2ca2d2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 04:13:18 -0500
Subject: [PATCH] [AMDGPU] Remove FeatureForceStoreSC0SC1
This was only used f
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/125836
>From 411774e0d3d6007130fb16be18fe9a37da4e3bfe Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 5 Feb 2025 05:50:12 -0500
Subject: [PATCH 1/2] [AMDGPU][MLIR] Replace gfx940 and gfx941 with gfx942 in
M
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/125827
>From 51b377df31cc5dcd9e1fd7e5f8ff69a1e4a25cbe Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 5 Feb 2025 04:45:26 -0500
Subject: [PATCH] [AMDGPU] Add missing gfx architectures to
AddFlangOffloadRunt
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126878
>From 731f633e66cf3118e5764ed4d0acbd794d2ca2d2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 04:13:18 -0500
Subject: [PATCH] [AMDGPU] Remove FeatureForceStoreSC0SC1
This was only used f
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126762
>From a80db3a9fe9654bc91b9377f8d38e6270380f9a2 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 11 Feb 2025 08:52:55 -0500
Subject: [PATCH] [AMDGPU][clang] Replace gfx940 and gfx941 with gfx942 in
cla
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126887
>From a5d359bb1a9b271316617fd84e10c64912e3c6a4 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 05:45:01 -0500
Subject: [PATCH] [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in
llvm
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126906
>From 5bfa81dbc27204e4a7b8b8cafc57bfbab56467d4 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 08:04:43 -0500
Subject: [PATCH] [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/125827
>From 51b377df31cc5dcd9e1fd7e5f8ff69a1e4a25cbe Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 5 Feb 2025 04:45:26 -0500
Subject: [PATCH] [AMDGPU] Add missing gfx architectures to
AddFlangOffloadRunt
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126887
>From a5d359bb1a9b271316617fd84e10c64912e3c6a4 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 05:45:01 -0500
Subject: [PATCH] [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in
llvm
https://github.com/lntue approved this pull request.
https://github.com/llvm/llvm-project/pull/126960
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@@ -199,3 +201,28 @@ const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID
CC,
return MCConstantExpr::create(0, Ctx);
}
+
+uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF) {
+ if (!CodeSizeInBytes.has_value()) {
+const GCNSubtarget &STM = MF.ge
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/126878
>From baa8adda226fea78f2fd595edadf57af72d7d049 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 12 Feb 2025 04:13:18 -0500
Subject: [PATCH] [AMDGPU] Remove FeatureForceStoreSC0SC1
This was only used f
@@ -248,7 +237,25 @@ else()
include_directories(SYSTEM ${MLIR_TABLEGEN_OUTPUT_DIR})
endif()
-option(FLANG_INCLUDE_RUNTIME "Build the runtime in-tree (deprecated; to be
replaced with LLVM_ENABLE_RUNTIMES=flang-rt)" ON)
+set(FLANG_INCLUDE_RUNTIME_default ON)
+if ("flang-rt" I
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/125826
>From e8d38e53f175c5d481c6774b330f0da15d234322 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 5 Feb 2025 04:19:00 -0500
Subject: [PATCH] [AMDGPU] Replace gfx940 and gfx941 with gfx942 in offload and
@@ -199,3 +201,28 @@ const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID
CC,
return MCConstantExpr::create(0, Ctx);
}
+
+uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF) {
+ if (!CodeSizeInBytes.has_value()) {
+const GCNSubtarget &STM = MF.ge
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/126981
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/127099
Backport c81139f417a209dbd2a4e06465483d4b0951a9ac
Requested by: @jhuber6
>From 5d310a324700bd34ecc369d3b0b66b3763a4d27a Mon Sep 17 00:00:00 2001
From: Sylvestre Ledru
Date: Thu, 13 Feb 2025 18:42:28 +0100
Subj
@@ -830,6 +832,37 @@ static void relaxPCHi20Lo12(Ctx &ctx, const InputSection
&sec, size_t i,
remove = 4;
}
+// Relax code sequence.
+// From:
+// pcaddu18i $ra, %call36(foo)
+// jirl $ra, $ra, 0
+// To:
+// b/bl foo
+static void relaxCall36(Ctx &ctx, const InputSecti
@@ -830,6 +832,37 @@ static void relaxPCHi20Lo12(Ctx &ctx, const InputSection
&sec, size_t i,
remove = 4;
}
+// Relax code sequence.
+// From:
+// pcaddu18i $ra, %call36(foo)
+// jirl $ra, $ra, 0
+// To:
+// b/bl foo
+static void relaxCall36(Ctx &ctx, const InputSecti
@@ -0,0 +1,61 @@
+# REQUIRES: loongarch
MaskRay wrote:
omit `-2` from the name
https://github.com/llvm/llvm-project/pull/123576
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rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/127129?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/127129
It does not change the estimate because getInstSizeInBytes() already
returns 0 for meta instructions, but added a test and early bail.
>From c0489545755c98dc2f87ffcd83af929816643074 Mon Sep 17 00:00:00 2001
Fro
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Stanislav Mekhanoshin (rampitec)
Changes
It does not change the estimate because getInstSizeInBytes() already
returns 0 for meta instructions, but added a test and early bail.
---
Full diff: https://github.com/llvm/llvm-project/pu
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/127144
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https://github.com/llvm/llvm-project/pull/127144
Backport 415607e
Requested by: @RossComputerGuy
>From 7d0590cc577b4b6ff243fb733c8c9ac0cc6dc221 Mon Sep 17 00:00:00 2001
From: Tristan Ross
Date: Thu, 13 Feb 2025 14:56:55 -0800
Subject: [PATCH] [ORC][unittests
llvmbot wrote:
@lhames What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/127144
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@@ -212,6 +212,8 @@ uint64_t SIProgramInfo::getFunctionCodeSize(const
MachineFunction &MF) {
uint64_t CodeSize = 0;
for (const MachineBasicBlock &MBB : MF) {
+CodeSize = alignTo(CodeSize, MBB.getAlignment());
rampitec wrote:
Pessimistic overestimate
https://github.com/lhames approved this pull request.
https://github.com/llvm/llvm-project/pull/127144
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https://github.com/llvm/llvm-project/pull/127142
None
>From d01d16815ade61a599b94bb18bc292e326767f15 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 13 Feb 2025 14:46:37 -0800
Subject: [PATCH] [AMDGPU] Respect MBB alignment in the getFunction
rampitec wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/127142?utm_source=stack-comment-downstack-mergeability-warning"
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Stanislav Mekhanoshin (rampitec)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/127142.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIProgramInfo.cpp (+2)
- (modified) llvm/test/CodeGen/AMDGPU/
@@ -199,3 +201,28 @@ const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID
CC,
return MCConstantExpr::create(0, Ctx);
}
+
+uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF) {
+ if (!CodeSizeInBytes.has_value()) {
+const GCNSubtarget &STM = MF.ge
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/127142
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https://github.com/Meinersbur updated
https://github.com/llvm/llvm-project/pull/124126
>From c515d13f0ad684763e6d76a87a610801482c15f4 Mon Sep 17 00:00:00 2001
From: Michael Kruse
Date: Fri, 24 Jan 2025 16:52:46 +0100
Subject: [PATCH 1/2] [Flang] Remove FLANG_INCLUDE_RUNTIME
---
flang/CMakeLis
https://github.com/Meinersbur updated
https://github.com/llvm/llvm-project/pull/121782
>From b05c9a033158aea459d51ff34b8ec47e72f85740 Mon Sep 17 00:00:00 2001
From: Michael Kruse
Date: Fri, 24 Jan 2025 16:51:27 +0100
Subject: [PATCH 1/2] [Flang-RT] Build libflang_rt.so
---
flang-rt/CMakeLists
@@ -212,6 +212,8 @@ uint64_t SIProgramInfo::getFunctionCodeSize(const
MachineFunction &MF) {
uint64_t CodeSize = 0;
for (const MachineBasicBlock &MBB : MF) {
+CodeSize = alignTo(CodeSize, MBB.getAlignment());
efriedma-quic wrote:
This is not the righ
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (llvmbot)
Changes
Backport 1083ec647f16314bcc9af8c4d6b11f50d288bca6
Requested by: @hvdijk
---
Patch is 32.04 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/127124.diff
11 Files Affected
slinder1 wrote:
I do have an llvm-reduce'd test case for downstream, just waiting on things to
flow down first. I can't actually add the test at all without a fix for the
duplicated metadata so didn't seem worth posting the review yet
https://github.com/llvm/llvm-project/pull/126148
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https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/127129
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https://github.com/petrhosek updated
https://github.com/llvm/llvm-project/pull/126960
>From 87587f925442d6369a7d511426a55ad50f3141ea Mon Sep 17 00:00:00 2001
From: Petr Hosek
Date: Wed, 12 Feb 2025 11:37:07 -0800
Subject: [PATCH] [libc] Move __LLVM_LIBC__ define to __llvm-libc-common.h
(#12687
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