MaskRay wrote:
Can you drop the trailing `.` in the subject?
https://github.com/llvm/llvm-project/pull/123743
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@@ -12879,13 +12879,33 @@ std::pair
SelectionDAG::UnrollVectorOverflowOp(
getBuildVector(NewOvVT, dl, OvScalars));
}
+bool SelectionDAG::areNonVolatileConsecutiveLoads(AtomicSDNode *LD,
arsenm wrote:
Unused? This is also just duplicat
@@ -1395,6 +1398,34 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N,
unsigned ResNo) {
SetSplitVector(SDValue(N, ResNo), Lo, Hi);
}
+void DAGTypeLegalizer::SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD) {
+ SDLoc dl(LD);
+
+ EVT MemoryVT = LD->getMemoryVT();
+ unsigne
@@ -5218,7 +5218,11 @@ void SelectionDAGBuilder::visitAtomicLoad(const LoadInst
&I) {
L = DAG.getPtrExtOrTrunc(L, dl, VT);
setValue(&I, L);
- DAG.setRoot(OutChain);
+
arsenm wrote:
Shouldn't need to touch this
https://github.com/llvm/llvm-project/pu
https://github.com/arsenm requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/120640
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@@ -194,8 +194,8 @@ bool BaseIndexOffset::contains(const SelectionDAG &DAG,
int64_t BitSize,
return false;
}
-/// Parses tree in Ptr for base, index, offset addresses.
-static BaseIndexOffset matchLSNode(const LSBaseSDNode *N,
+template
+static BaseIndexOffset matchSDNode(
https://github.com/ylzsx edited https://github.com/llvm/llvm-project/pull/123702
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https://github.com/ylzsx edited https://github.com/llvm/llvm-project/pull/123715
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https://github.com/ylzsx edited https://github.com/llvm/llvm-project/pull/123730
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https://github.com/ylzsx edited https://github.com/llvm/llvm-project/pull/123680
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rampitec wrote:
> > Is there any way at all to test it?
>
> Many shuffle tests were added in
> [7786266](https://github.com/llvm/llvm-project/commit/7786266dc7b4e89feadcb01ff21f9e3cf2022a6b),
> this shows they are a no-op. The expected test changes from this are in
> #123711
OK, I see. LGTM.
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/123711
>From 0a3791a40d76d6d80196a0fb27222414b5d73332 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 18 Jan 2025 08:19:10 +0700
Subject: [PATCH] AMDGPU: Custom lower 32-bit element shuffles
This is so we can
arsenm wrote:
> Is there any way at all to test it?
Many shuffle tests were added in 7786266dc7b4e89feadcb01ff21f9e3cf2022a6b, this
shows they are a no-op. The expected test changes from this are in #123711
https://github.com/llvm/llvm-project/pull/123711
__
@@ -1150,6 +1152,58 @@ void LoongArch::tlsdescToLe(uint8_t *loc, const
Relocation &rel,
}
}
+// Try GOT indirection to PC relative optimization when relaxation is enabled.
+// From:
+// * pcalau12i $a0, %got_pc_hi20(sym_got)
+// * ld.w/d$a0, $a0, %got_pc_lo12(sym_got)
@@ -1150,6 +1152,58 @@ void LoongArch::tlsdescToLe(uint8_t *loc, const
Relocation &rel,
}
}
+// Try GOT indirection to PC relative optimization when relaxation is enabled.
+// From:
+// * pcalau12i $a0, %got_pc_hi20(sym_got)
+// * ld.w/d$a0, $a0, %got_pc_lo12(sym_got)
https://github.com/ylzsx edited https://github.com/llvm/llvm-project/pull/123677
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@@ -1395,6 +1398,34 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N,
unsigned ResNo) {
SetSplitVector(SDValue(N, ResNo), Lo, Hi);
}
+void DAGTypeLegalizer::SplitVecRes_ATOMIC_LOAD(AtomicSDNode *LD) {
+ SDLoc dl(LD);
+
+ EVT MemoryVT = LD->getMemoryVT();
+ unsigne
@@ -7071,14 +7071,23 @@ static SDValue LowerAsSplatVectorLoad(SDValue SrcOp,
MVT VT, const SDLoc &dl,
}
// Recurse to find a LoadSDNode source and the accumulated ByteOffest.
-static bool findEltLoadSrc(SDValue Elt, LoadSDNode *&Ld, int64_t &ByteOffset) {
- if (ISD::isNON_EX
https://github.com/ylzsx edited https://github.com/llvm/llvm-project/pull/123600
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@@ -2639,6 +2639,10 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i
https://github.com/ylzsx edited https://github.com/llvm/llvm-project/pull/123743
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