@@ -489,6 +489,90 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N,
unsigned RegClassID) {
CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs);
}
+void AMDGPUDAGToDAGISel::SelectVectorShuffle(SDNode *N) {
+ EVT VT = N->getValueType(0);
+ EVT E
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/123695
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/123711
This is so we can try to make use of v_pk_mov_b32 when available.
Note this currently has little observable effect. The combiner
will undo the common extract of shuffle pattern. The lack
of test changes should dem
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
This is so we can try to make use of v_pk_mov_b32 when available.
Note this currently has little observable effect. The combiner
will undo the common extract of shuffle pattern. The lack
of test chan
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/123711?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/123711
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arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/123712?utm_source=stack-comment-downstack-mergeability-warning";
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Previously this combine would undo AMDGPU's new custom legalization of
wide vector shuffles into 2 element pieces. The comment also
states that this combine is only done before legalization,
but the
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/123695
>From b85cc524ef390d2680359d2ccc7085af11eb2eaf Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 21 Jan 2025 06:30:07 +
Subject: [PATCH] [AMDGPU][NewPM] Port SILowerWWMCopies to NPM
---
llvm/lib/Targe
https://github.com/optimisan ready_for_review
https://github.com/llvm/llvm-project/pull/123695
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Akshat Oke (optimisan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/123695.diff
6 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPU.h (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.
llvmbot wrote:
@llvm/pr-subscribers-lld
Author: Zhaoxin Yang (ylzsx)
Changes
Support TLSDESC to initial-exec or local-exec optimizations. Introduce a new
hook RE_LOONGARCH_RELAX_TLS_GD_TO_IE_PAGE_PC and use existing
R_RELAX_TLS_GD_TO_IE_ABS to support TLSDESC => IE, while use existing
R
https://github.com/ylzsx created
https://github.com/llvm/llvm-project/pull/123715
Support TLSDESC to initial-exec or local-exec optimizations. Introduce a new
hook RE_LOONGARCH_RELAX_TLS_GD_TO_IE_PAGE_PC and use existing
R_RELAX_TLS_GD_TO_IE_ABS to support TLSDESC => IE, while use existing
R_
@@ -23172,6 +23172,11 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode
*N) {
}
if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
+ // TODO: Check if shuffle mask is legal?
+ if (LegalOperations && TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VecVT)
&&
@@ -23172,6 +23172,11 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode
*N) {
}
if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
+ // TODO: Check if shuffle mask is legal?
+ if (LegalOperations && TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VecVT)
&&
https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/123715
>From dff3031fdb2ca3755b73e3b81e56f8008a409470 Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Fri, 3 Jan 2025 14:29:17 +0800
Subject: [PATCH 1/6] [lld][LoongArch] Implement TLSDESC GD/LD to IE/LE.
Support TLSDE
ylzsx wrote:
I have submitted all the patches related to relaxation in lld for LoongArch.
Below is a list for peer review:
* users/ylzsx/r-got-to-pcrel
│ https://github.com/llvm/llvm-project/pull/123743
│
* users/ylzsx/r-tlsdesc-to-iele-relax
│ https://github.com/llvm/llvm-project/pull
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/123711
>From 6434af5c57940d376b1acc281e090346a6a5bc22 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 18 Jan 2025 08:19:10 +0700
Subject: [PATCH] AMDGPU: Custom lower 32-bit element shuffles
This is so we can
https://github.com/jeanPerier updated
https://github.com/llvm/llvm-project/pull/123177
>From 137705661c184ea1530982c19163341933ab421e Mon Sep 17 00:00:00 2001
From: Jean Perier
Date: Wed, 15 Jan 2025 09:09:53 -0800
Subject: [PATCH 1/4] [mlir][LLVM] add argument and result attributes to
llvm.ca
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/123695
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github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 3fa2cf6b1a6a4509635c2c90bed2876beb748110
7e7ba17845cd66e3fcbbe19097f4a60407e13ef4 --e
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Nathan Ridge (HighCommander4)
Changes
Fixes https://github.com/clangd/clangd/issues/1249
---
Full diff: https://github.com/llvm/llvm-project/pull/123818.diff
2 Files Affected:
- (modified) clang/lib/Sema/SemaCodeComplete.cpp (+18-7)
-
https://github.com/HighCommander4 created
https://github.com/llvm/llvm-project/pull/123818
Fixes https://github.com/clangd/clangd/issues/1249
>From 58029449d63af7f452820dd02aba0d10134f588c Mon Sep 17 00:00:00 2001
From: Nathan Ridge
Date: Tue, 21 Jan 2025 15:56:27 -0500
Subject: [PATCH] [clang
https://github.com/s-perron approved this pull request.
LGTM. The SPIR-V code seems correct. It would be useful to have a SPIR-V
specific test.
https://github.com/llvm/llvm-project/pull/123411
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https://github.com/s-perron edited
https://github.com/llvm/llvm-project/pull/123411
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s-perron wrote:
Could we add a test for SPIR-V to make sure it gets the correct address space
as well? They have different target info, so the are different code paths.
https://github.com/llvm/llvm-project/pull/123411
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https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/123775
None
>From 85c7ec7fee92ba634f3d2bec502eab94d4fbf18e Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Fri, 9 Feb 2024 15:56:02 +
Subject: [PATCH 1/4] Add TreePattern constructor that takes multiple
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From 4205f3f94a8a991919569a02e549cb7d649c876b Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From 4205f3f94a8a991919569a02e549cb7d649c876b Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120598
>From a7fb95e250eac58c806161e7ffc666779606d217 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic
load
Vector ty
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120598
>From a7fb95e250eac58c806161e7ffc666779606d217 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic
load
Vector ty
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From ff979b4758b6d7b3120bd656726d273414c44170 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 4698589155b60abda2caefd8664599850d084d6e Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atom
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120640
>From 1ac2df790916fb43a60f38ffbaa4c9b8c2f63771 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 16:25:55 -0500
Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for
atomic load
Vecto
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From ff979b4758b6d7b3120bd656726d273414c44170 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From 4205f3f94a8a991919569a02e549cb7d649c876b Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120640
>From 1ac2df790916fb43a60f38ffbaa4c9b8c2f63771 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 16:25:55 -0500
Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for
atomic load
Vecto
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 4698589155b60abda2caefd8664599850d084d6e Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atom
@@ -5901,6 +5904,30 @@ SDValue
DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
N->getOperand(1), N->getOperand(2));
}
+SDValue DAGTypeLegalizer::WidenVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
+ SmallVector LdChain; // Chain for the series of loa
https://github.com/HighCommander4 edited
https://github.com/llvm/llvm-project/pull/123818
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https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120598
>From 5254725d2f49042d87194074e23c29d2d2dc3525 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic
load
Vector ty
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From 9fde3b59ab60cf55ad324b4348aa60bde6ae5706 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 846ab2e6caad370afa04fe217d18d55d524f3799 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atom
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 647a59b75785b5b6b930687f26397cd06c44f93b Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120598
>From 5254725d2f49042d87194074e23c29d2d2dc3525 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic
load
Vector ty
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120640
>From b36e103034ad5cbb6cea31ce1148518d7ea136ae Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 16:25:55 -0500
Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for
atomic load
Vecto
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From 9fde3b59ab60cf55ad324b4348aa60bde6ae5706 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 11b950d871756b65d4c58e59b22a6af595f0cd0c Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120598
>From 5254725d2f49042d87194074e23c29d2d2dc3525 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic
load
Vector ty
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120640
>From b36e103034ad5cbb6cea31ce1148518d7ea136ae Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 16:25:55 -0500
Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for
atomic load
Vecto
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From 9fde3b59ab60cf55ad324b4348aa60bde6ae5706 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 846ab2e6caad370afa04fe217d18d55d524f3799 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atom
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 647a59b75785b5b6b930687f26397cd06c44f93b Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 647a59b75785b5b6b930687f26397cd06c44f93b Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 846ab2e6caad370afa04fe217d18d55d524f3799 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atom
@@ -146,6 +146,47 @@ define <1 x i64> @atomic_vec1_i64_align(ptr %x) nounwind {
ret <1 x i64> %ret
}
+define <2 x i8> @atomic_vec2_i8(ptr %x) {
+; CHECK3-LABEL: atomic_vec2_i8:
+; CHECK3: ## %bb.0:
+; CHECK3-NEXT:movzwl (%rdi), %eax
+; CHECK3-NEXT:retq
+;
+; CH
https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/123411
>From 6aba475e4af789fc03594560ad9937e3502cce51 Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Fri, 17 Jan 2025 13:31:01 -0800
Subject: [PATCH 1/2] [HLSL] Add address space `hlsl_constant(2)` for constant
buff
hekota wrote:
I have added SPIR-V variants of the 3 codegen tests.
https://github.com/llvm/llvm-project/pull/123411
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/123711
>From 4e1bdb492246adacd90c42b0590613e040268e1a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 18 Jan 2025 08:19:10 +0700
Subject: [PATCH] AMDGPU: Custom lower 32-bit element shuffles
This is so we can
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From b0364eefcd22e368bab088222d052f71ef2b835e Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
@@ -455,14 +456,22 @@ void createHostLayoutStructForBuffer(Sema &S,
HLSLBufferDecl *BufDecl) {
LS->setImplicit(true);
LS->startDefinition();
- for (const Decl *D : BufDecl->decls()) {
-const VarDecl *VD = dyn_cast(D);
+ for (Decl *D : BufDecl->decls()) {
+VarDec
https://github.com/preames approved this pull request.
LGTM
I suspect we'll want to refine the profitability here over the time, but this
seems reasonable as a stepping stone.
https://github.com/llvm/llvm-project/pull/123712
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https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From b0364eefcd22e368bab088222d052f71ef2b835e Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
@@ -83,6 +83,7 @@ const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr32_uptr
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr64
llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_groupshared
+llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_constant
--
rampitec wrote:
Is there any way at all to test it?
https://github.com/llvm/llvm-project/pull/123711
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https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120598
>From a847ecfa366a17853e425a5fd94edb668396b446 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic
load
Vector ty
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From f4d372c660d9c5abe4e60aca91d455c5c376a25e Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120640
>From a14a025133cc1e18bc1d554d3b0d9961f3696131 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 16:25:55 -0500
Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for
atomic load
Vecto
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120598
>From a847ecfa366a17853e425a5fd94edb668396b446 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic
load
Vector ty
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 02d1d2da5ed69cf3d577b11ad4563c5d1bfc2d22 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 2af4d7c2efd07dc96e93017c3684f6aeb73be9e8 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120640
>From a14a025133cc1e18bc1d554d3b0d9961f3696131 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 16:25:55 -0500
Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for
atomic load
Vecto
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From f4d372c660d9c5abe4e60aca91d455c5c376a25e Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120640
>From a14a025133cc1e18bc1d554d3b0d9961f3696131 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 16:25:55 -0500
Subject: [PATCH] [SelectionDAG][X86] Split via Concat vector types for
atomic load
Vecto
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 6f50ac7470ddea05e4cddfd51aab3d9a69736767 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atom
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 02d1d2da5ed69cf3d577b11ad4563c5d1bfc2d22 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120385
>From 02d1d2da5ed69cf3d577b11ad4563c5d1bfc2d22 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:37:17 -0500
Subject: [PATCH] [SelectionDAG] Legalize <1 x T> vector types for atomic load
`load atomic
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120716
>From f4d372c660d9c5abe4e60aca91d455c5c376a25e Mon Sep 17 00:00:00 2001
From: jofrn
Date: Fri, 20 Dec 2024 06:14:28 -0500
Subject: [PATCH] [AtomicExpand] Add bitcasts when expanding load atomic vector
AtomicExpan
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120386
>From 6f50ac7470ddea05e4cddfd51aab3d9a69736767 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:38:23 -0500
Subject: [PATCH] [X86] Manage atomic load of fp -> int promotion in DAG
When lowering atom
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 2af4d7c2efd07dc96e93017c3684f6aeb73be9e8 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120598
>From a847ecfa366a17853e425a5fd94edb668396b446 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Thu, 19 Dec 2024 11:19:39 -0500
Subject: [PATCH] [SelectionDAG][X86] Widen <2 x T> vector types for atomic
load
Vector ty
https://github.com/jofrn updated
https://github.com/llvm/llvm-project/pull/120387
>From 2af4d7c2efd07dc96e93017c3684f6aeb73be9e8 Mon Sep 17 00:00:00 2001
From: jofrn
Date: Wed, 18 Dec 2024 03:40:32 -0500
Subject: [PATCH] [X86] Add atomic vector tests for unaligned >1 sizes.
Unaligned atomic ve
@@ -5907,6 +5910,30 @@ SDValue
DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
N->getOperand(1), N->getOperand(2));
}
+SDValue DAGTypeLegalizer::WidenVecRes_ATOMIC_LOAD(AtomicSDNode *N) {
+ SmallVector LdChain; // Chain for the series of loa
https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/123411
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@@ -42,6 +42,7 @@ static const unsigned DirectXAddrSpaceMap[] = {
0, // ptr32_uptr
0, // ptr64
3, // hlsl_groupshared
+2, // hlsl_constant
hekota wrote:
Yes, not updating all of the maps produces a compile error.
https://github.com/llvm/llvm-p
https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/123730
>From 187759562d861034a79cd8c4ee4ab063bba5f4ff Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Sat, 4 Jan 2025 15:03:47 +0800
Subject: [PATCH 1/2] Support relaxation during TLSDESC GD/LD to IE/LE
conversion.
Co
llvmbot wrote:
@llvm/pr-subscribers-lld
Author: Zhaoxin Yang (ylzsx)
Changes
In LoongArch, this optimization is only supported when relaxation is enabled.
From:
* pcalau12i $a0, %got_pc_hi20(sym_got)
* ld.w/d $a0, $a0, %got_pc_lo12(sym_got)
To:
* pcalau12i $a0, %pc_hi20(sym)
* addi.w/d $a0
llvmbot wrote:
@llvm/pr-subscribers-lld-elf
Author: Zhaoxin Yang (ylzsx)
Changes
In LoongArch, this optimization is only supported when relaxation is enabled.
From:
* pcalau12i $a0, %got_pc_hi20(sym_got)
* ld.w/d $a0, $a0, %got_pc_lo12(sym_got)
To:
* pcalau12i $a0, %pc_hi20(sym)
* addi.w/d
https://github.com/ylzsx created
https://github.com/llvm/llvm-project/pull/123743
In LoongArch, this optimization is only supported when relaxation is enabled.
From:
* pcalau12i $a0, %got_pc_hi20(sym_got)
* ld.w/d $a0, $a0, %got_pc_lo12(sym_got)
To:
* pcalau12i $a0, %pc_hi20(sym)
* addi.w/d $a0,
https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/123715
>From dff3031fdb2ca3755b73e3b81e56f8008a409470 Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Fri, 3 Jan 2025 14:29:17 +0800
Subject: [PATCH 1/5] [lld][LoongArch] Implement TLSDESC GD/LD to IE/LE.
Support TLSDE
@@ -489,6 +489,90 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N,
unsigned RegClassID) {
CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs);
}
+void AMDGPUDAGToDAGISel::SelectVectorShuffle(SDNode *N) {
+ EVT VT = N->getValueType(0);
+ EVT E
https://github.com/ylzsx created
https://github.com/llvm/llvm-project/pull/123730
Complement https://github.com/llvm/llvm-project/pull/123715. When relaxation
enable, remove redundant NOPs.
>From ddb64ee49845b302df8ea50546164cceb87cf288 Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Sat, 4
llvmbot wrote:
@llvm/pr-subscribers-lld-elf
@llvm/pr-subscribers-lld
Author: Zhaoxin Yang (ylzsx)
Changes
Complement https://github.com/llvm/llvm-project/pull/123715. When relaxation
enable, remove redundant NOPs.
---
Full diff: https://github.com/llvm/llvm-project/pull/123730.diff
2 F
https://github.com/jeanPerier updated
https://github.com/llvm/llvm-project/pull/123177
>From 137705661c184ea1530982c19163341933ab421e Mon Sep 17 00:00:00 2001
From: Jean Perier
Date: Wed, 15 Jan 2025 09:09:53 -0800
Subject: [PATCH 1/4] [mlir][LLVM] add argument and result attributes to
llvm.ca
Author: Jacob Lalonde
Date: 2025-01-21T19:54:42-08:00
New Revision: 7aac81a4e30f9e46907a60009ec051473089319e
URL:
https://github.com/llvm/llvm-project/commit/7aac81a4e30f9e46907a60009ec051473089319e
DIFF:
https://github.com/llvm/llvm-project/commit/7aac81a4e30f9e46907a60009ec051473089319e.diff
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/123711
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https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/123715
>From dff3031fdb2ca3755b73e3b81e56f8008a409470 Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Fri, 3 Jan 2025 14:29:17 +0800
Subject: [PATCH 1/7] [lld][LoongArch] Implement TLSDESC GD/LD to IE/LE.
Support TLSDE
@@ -1150,6 +1152,58 @@ void LoongArch::tlsdescToLe(uint8_t *loc, const
Relocation &rel,
}
}
+// Try GOT indirection to PC relative optimization when relaxation is enabled.
+// From:
+// * pcalau12i $a0, %got_pc_hi20(sym_got)
+// * ld.w/d$a0, $a0, %got_pc_lo12(sym_got)
@@ -1150,6 +1152,58 @@ void LoongArch::tlsdescToLe(uint8_t *loc, const
Relocation &rel,
}
}
+// Try GOT indirection to PC relative optimization when relaxation is enabled.
+// From:
+// * pcalau12i $a0, %got_pc_hi20(sym_got)
+// * ld.w/d$a0, $a0, %got_pc_lo12(sym_got)
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