arsenm wrote:
### Merge activity
* **Jan 16, 8:30 PM EST**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/122460).
https://github.com/llvm/llvm-project/pull/122460
_
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/122460
>From 3860dfc5fbff94649a075f2177be235be7c02978 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 10 Jan 2025 14:57:24 +0700
Subject: [PATCH 1/2] AMDGPU: Implement isExtractVecEltCheap
Once again we have e
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/122460
>From 81351fd3f40b3352612b0f5740de30af638c238b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 10 Jan 2025 14:57:24 +0700
Subject: [PATCH 1/2] AMDGPU: Implement isExtractVecEltCheap
Once again we have e
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/122460
>From 924abbb3903a00f55cdee361985c74982c492963 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 10 Jan 2025 14:57:24 +0700
Subject: [PATCH 1/2] AMDGPU: Implement isExtractVecEltCheap
Once again we have e
@@ -1949,6 +1949,13 @@ bool SITargetLowering::isExtractSubvectorCheap(EVT
ResVT, EVT SrcVT,
return Index == 0;
}
+bool SITargetLowering::isExtractVecEltCheap(EVT VT, unsigned Index) const {
+ // TODO: This should be more aggressive, particular for 16-bit element
+ // vect
@@ -1949,6 +1949,13 @@ bool SITargetLowering::isExtractSubvectorCheap(EVT
ResVT, EVT SrcVT,
return Index == 0;
}
+bool SITargetLowering::isExtractVecEltCheap(EVT VT, unsigned Index) const {
+ // TODO: This should be more aggressive, particular for 16-bit element
+ // vect
@@ -1949,6 +1949,13 @@ bool SITargetLowering::isExtractSubvectorCheap(EVT
ResVT, EVT SrcVT,
return Index == 0;
}
+bool SITargetLowering::isExtractVecEltCheap(EVT VT, unsigned Index) const {
+ // TODO: This should be more aggressive, particular for 16-bit element
+ // vect
@@ -1949,6 +1949,13 @@ bool SITargetLowering::isExtractSubvectorCheap(EVT
ResVT, EVT SrcVT,
return Index == 0;
}
+bool SITargetLowering::isExtractVecEltCheap(EVT VT, unsigned Index) const {
+ // TODO: This should be more aggressive, particular for 16-bit element
+ // vect
https://github.com/jayfoad approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/122460
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https://github.com/jayfoad edited
https://github.com/llvm/llvm-project/pull/122460
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/122460
>From ea6a8ce50fbd64222bd897080eed662aaba15e43 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 10 Jan 2025 14:57:24 +0700
Subject: [PATCH] AMDGPU: Implement isExtractVecEltCheap
Once again we have exces
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/122460
>From b93cb29230bde4ea2bb6577c56af81305f617920 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 10 Jan 2025 14:57:24 +0700
Subject: [PATCH] AMDGPU: Implement isExtractVecEltCheap
Once again we have exces
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/122460
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Once again we have excessive TLI hooks with bad defaults. Permit this
for 32-bit element vectors, which are just use-different-register.
We should permit 16-bit vectors as cheap with legal packed ins
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/122460?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/122460
Once again we have excessive TLI hooks with bad defaults. Permit this
for 32-bit element vectors, which are just use-different-register.
We should permit 16-bit vectors as cheap with legal packed instructions,
but
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