https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
wangpc-pp wrote:
https://github.com/llvm/llvm-project/pull/97708 is splitted out for adding
`FeaturePredictableSelectIsExpensive`.
https://github.com/llvm/llvm-project/pull/80124
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wangpc-pp wrote:
Ping.
I'd like to push this forward because we don't take branch probabilities into
consideration now.
Example: https://godbolt.org/z/doGhYadKM
We should use branches instead of selects in this case and this patch (the
enabling of SelectOpt) will optimize this.
`clang -O3 -marc
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/80124
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
wangpc-pp wrote:
> > > JFYI, I don't find the AArch64 data particularly convincing for RISCV.
> > > The magnitude of the change even on AArch64 is small, and could easily be
> > > swung one direction or the other by differences in implementation between
> > > the backends.
> >
> >
> > Yeah!
@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt
+EnableSelectOpt("riscv-select-opt", cl::Hidden,
wangpc-pp wrote:
Most of the added pas
topperc wrote:
> > JFYI, I don't find the AArch64 data particularly convincing for RISCV. The
> > magnitude of the change even on AArch64 is small, and could easily be swung
> > one direction or the other by differences in implementation between the
> > backends.
>
> Yeah! The result will dif
@@ -1046,6 +1046,14 @@ def FeatureFastUnalignedAccess
def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
"UsePostRAScheduler", "true", "Schedule again after register allocation">;
+def FeaturePredictableSelectIsExpensive
+ : SubtargetFeature<"predictabl
@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt
+EnableSelectOpt("riscv-select-opt", cl::Hidden,
topperc wrote:
> I think the impact wo
wangpc-pp wrote:
Ping. Any more concerns?
https://github.com/llvm/llvm-project/pull/80124
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@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt
+EnableSelectOpt("riscv-select-opt", cl::Hidden,
wangpc-pp wrote:
@topperc WDYT?
https
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/80124
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@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt
+EnableSelectOpt("riscv-select-opt", cl::Hidden,
wangpc-pp wrote:
Yeah, this point make
@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt
+EnableSelectOpt("riscv-select-opt", cl::Hidden,
topperc wrote:
But we added a bunch of
@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt
+EnableSelectOpt("riscv-select-opt", cl::Hidden,
wangpc-pp wrote:
We have already disab
@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering(
cl::desc("Enable load clustering in the machine scheduler"),
cl::init(false));
+static cl::opt
+EnableSelectOpt("riscv-select-opt", cl::Hidden,
topperc wrote:
If no in tree targets u
https://github.com/topperc deleted
https://github.com/llvm/llvm-project/pull/80124
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@@ -1046,6 +1046,14 @@ def FeatureFastUnalignedAccess
def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
"UsePostRAScheduler", "true", "Schedule again after register allocation">;
+def FeaturePredictableSelectIsExpensive
+ : SubtargetFeature<"predictabl
wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/80124
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Targ
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/80124
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https://github.com/dtcxzyw requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/80124
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@@ -451,6 +456,9 @@ void RISCVPassConfig::addIRPasses() {
}
TargetPassConfig::addIRPasses();
+
+ if (getOptLevel() == CodeGenOptLevel::Aggressive && EnableSelectOpt)
dtcxzyw wrote:
> Failed Tests (1):
LLVM :: CodeGen/RISCV/O3-pipeline.ll
Please update
wangpc-pp wrote:
Gentle ping.
https://github.com/llvm/llvm-project/pull/80124
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH] Move after addIRPasses
Created using spr 1.3.4
---
llvm/lib/Target/R
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