[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -2504,5 +2504,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { Options.LoadSizes = {8, 4, 2, 1}; else Options.LoadSizes = {4, 2, 1}; + if (IsZeroCmp && ST->hasVInstructions()) { +unsigned RealMinVLen = ST->getRealMinVLen() / 8;

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -3186,190 +3186,24 @@ define i32 @bcmp_size_16(ptr %s1, ptr %s2) nounwind { ; ; CHECK-ALIGNED-RV32-V-LABEL: bcmp_size_16: ; CHECK-ALIGNED-RV32-V: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-V-NEXT:lbu a2, 1(a0) -; CHECK-ALIGNED-RV32-V-NEXT:lbu a3, 0(a0) -; CHECK-AL

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/114517 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: Pengcheng Wang (wangpc-pp) Changes --- Patch is 404.53 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/114517.diff 4 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVISelLowe

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/114517 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits