wangpc-pp wrote:
Thanks for evaluating this! The data is very helpful! @michaelmaitland
> Given @michaelmaitland's data, @wangpc-pp the burden shifts to you to clearly
> justify which cases this is profitable and figure out how to selectively
> enable only in profitable cases. I agree with @m
preames wrote:
Given @michaelmaitland's data, @wangpc-pp the burden shifts to you to clearly
justify which cases this is profitable and figure out how to selectively enable
only in profitable cases. I agree with @michaelmaitland's conclusion that this
should not move forward otherwise.
@m
michaelmaitland wrote:
I measured this patch on spec for an in-order and an out-of-order core.
For the out-of-order core, 557.xz_r saw a regression.
For the in-order core, I see regression on 456.hmmer and 458.sjeng.
I saw no other significant improvements or regressions.
These findings, comb
@@ -727,27 +728,49 @@ define void @buildvec_seq_v4i16_v2i32(ptr %x) {
}
define void @buildvec_vid_step1o2_v4i32(ptr %z0, ptr %z1, ptr %z2, ptr %z3,
ptr %z4, ptr %z5, ptr %z6) {
-; CHECK-LABEL: buildvec_vid_step1o2_v4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT:vsetivli zer
https://github.com/mshockwave edited
https://github.com/llvm/llvm-project/pull/115858
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https://github.com/mshockwave approved this pull request.
LGTM . I do have some minor questions but they're not blocking.
https://github.com/llvm/llvm-project/pull/115858
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@@ -354,30 +354,51 @@ define @select_nxv32i32( %a, https://github.com/llvm/llvm-project/pull/115858
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/115858
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wangpc-pp wrote:
I added two experimental options: `-riscv-disable-latency-heuristic` and
`-riscv-should-track-lane-masks` and evaluated the statistics
(`regalloc.NumSpills`/`regalloc.NumReloads`) on llvm-test-suite (option: `-O3
-march=rva23u64`):
1. `-riscv-disable-latency-heuristic=true` an
mshockwave wrote:
> This helps reduce register pressure for some cases.
Is it possible to provide some numbers to back this up? Preferably using some
well known benchmarks like SPEC and/or llvm-test-suite
https://github.com/llvm/llvm-project/pull/115858
michaelmaitland wrote:
For the recent scheduler patches, the common theme is we saw another target did
something brought that functionality to RISC-V. How do we know that these
changes are sensible defaults for RISC-V cores? Are you making measurements on
any cores? Are they in order, out of o
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/115858
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llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
Changes
This helps reduce register pressure for some cases.
---
Patch is 7.18 MiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/115858.diff
465 Files Affecte
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/115858
This helps reduce register pressure for some cases.
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