shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/149631?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149631
This is a partial support because some other instructions have not been
upstreamed yet.
>From 76cf51351db63757e8caa1cf6c542dfd6d110978 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 21:52:3
shiltian wrote:
### Merge activity
* **Jul 18, 4:46 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149528).
https://github.com/llvm/llvm-project/pull/149528
___
shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/149528?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149528
Co-authored-by: Mekhanoshin, Stanislav
Co-authored-by: Foad, Jay
>From 74b03a1349712eeb578499f42e64d72b47bce24a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:36:56 -0400
Subject: [PATC
shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/149518?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149518
Co-authored-by: Mekhanoshin, Stanislav
>From c38e27b115c2fe9255eaaa89e9e83a48bc6edb23 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for
https://github.com/shiltian approved this pull request.
LGTM. @alexey-bataev WDYT?
https://github.com/llvm/llvm-project/pull/146405
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@@ -4007,7 +4007,8 @@ SDValue
AMDGPUTargetLowering::performIntrinsicWOChainCombine(
case Intrinsic::amdgcn_rcp_legacy:
case Intrinsic::amdgcn_rsq_legacy:
case Intrinsic::amdgcn_rsq_clamp:
- case Intrinsic::amdgcn_tanh: {
+ case Intrinsic::amdgcn_tanh:
+ case Intrinsic
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149450
>From 487881ca26a91b76e24e10e152aa98fedf19414a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 00:26:15 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_prng_b32` on gfx1250
Co-authored-by:
shiltian wrote:
> LGTM. But has the builtin definition already been added in clang?
Yes, when we did gfx950 support. This is not really a new instruction in
gfx1250.
https://github.com/llvm/llvm-project/pull/149450
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@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
-; xUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250
-mattr=+real-true16 %s -o - | FileCheck -check-prefix=SDAG-REAL16 %s
+; RUN: llc -global-isel=
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149360
>From aa16e59e51da91e8fe16f36f76a3e378edf58903 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 13:03:14 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_f32` on gfx1250
Co-authored-by:
shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/149360?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149360
Co-authored-by: Mekhanoshin, Stanislav
>From 2fa6c545f78a345feb30c1ac27e9874106b5870c Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 13:03:14 -0400
Subject: [PATCH] [AMDGPU] Add support for
shiltian wrote:
### Merge activity
* **Jul 17, 12:41 PM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149241).
https://github.com/llvm/llvm-project/pull/149241
__
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149241
>From 49f17c4881a35563c920bef2e9f3c7218a503a23 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 16 Jul 2025 23:48:48 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sin_bf16` on gfx1250
Co-authored-by:
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149241
>From 74b87c9261c594d21208dbc122b86a8d8e84310d Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 16 Jul 2025 23:48:48 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sin_bf16` on gfx1250
Co-authored-by:
shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/149241?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149241
Co-authored-by: Mekhanoshin, Stanislav
>From 44ec01ff5c2dbca8c7e3b8f07cd067db37149603 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 16 Jul 2025 23:48:48 -0400
Subject: [PATCH] [AMDGPU] Add support for
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/148921
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shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148921?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/148921
None
>From 6893db624adb4a4f76ea6b7acfb8b30387f8bfc5 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 15 Jul 2025 14:31:34 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sqrt_bf16` on gfx1250
---
llv
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/148727
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@@ -447,14 +447,42 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N,
unsigned RegClassID) {
return;
}
+ bool IsGCN = CurDAG->getSubtarget().getTargetTriple().isAMDGCN();
+ if (IsGCN && Subtarget->has64BitLiterals() && VT.getSizeInBits() == 64 &&
+ CurDAG->
shiltian wrote:
Even after I expanded all folded files, when I search for `__kmpc_parallel_60`,
my browser only shows three matches. Did I miss anything here?
https://github.com/llvm/llvm-project/pull/146405
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@@ -45,7 +45,24 @@ using namespace ompx;
namespace {
-uint32_t determineNumberOfThreads(int32_t NumThreadsClause) {
+void num_threads_strict_error(int32_t nt_strict, int32_t nt_severity,
shiltian wrote:
Please use LLVM code style for device runtime.
https:/
https://github.com/shiltian commented:
There doesn't seem to be any test case for the new added `__kmpc_parallel_60`.
If it is orthogonal to the `__kmpc_push_num_threads_strict` change, I'd prefer
to make it a separate PR and have tests there.
https://github.com/llvm/llvm-project/pull/146405
_
shiltian wrote:
### Merge activity
* **Jun 30, 11:47 AM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/146305).
https://github.com/llvm/llvm-project/pull/146305
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https://github.com/llvm/llvm-project/pull/146305
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/146305
>From 165b8e3d9d18350e2d976aac8614f093f6189a6a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:02 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250
Co-authored-
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/146305
>From 165b8e3d9d18350e2d976aac8614f093f6189a6a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:02 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250
Co-authored-
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/146305
>From f236297e3e4f40929dd214f6a3a92f28fc160cd1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:02 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250
Co-authored-
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/146305
>From f236297e3e4f40929dd214f6a3a92f28fc160cd1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:02 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250
Co-authored-
shiltian wrote:
> > Co-authored-by: Shilei Tian [i...@tianshilei.me](mailto:i...@tianshilei.me)
>
> Co authored by yourself?
Same as its parent.
https://github.com/llvm/llvm-project/pull/146305
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shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146305?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/146305
Co-authored-by: Shilei Tian
>From cb1103c52ec9c8bf1dac1f27136e4d524ce3cc4c Mon Sep 17 00:00:00 2001
From: "Mekhanoshin, Stanislav"
Date: Sun, 29 Jun 2025 23:19:25 -0400
Subject: [PATCH] [AMDGPU] Add support f
shiltian wrote:
### Merge activity
* **Jun 25, 8:56 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/145753).
https://github.com/llvm/llvm-project/pull/145753
___
shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145747?utm_source=stack-comment-downstack-mergeability-warning"
shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145753?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/145753
Co-authored-by: Shilei Tian
>From 76ed9609ab498504f7bd557d9703cb5d5f06b043 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 25 Jun 2025 13:56:12 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_pk_
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/145753
>From 5d44b53a20029b6f216bd18f47f49a9e873613e7 Mon Sep 17 00:00:00 2001
From: "Mekhanoshin, Stanislav"
Date: Wed, 25 Jun 2025 13:56:12 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_pk_f16_bf8` on gfx12
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/145747
>From cd383faea1421c6b048fc709685d56e3483c72f5 Mon Sep 17 00:00:00 2001
From: "Mekhanoshin, Stanislav"
Date: Wed, 25 Jun 2025 13:27:57 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_pk_f16_fp8` on gfx12
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/145747
>From cd383faea1421c6b048fc709685d56e3483c72f5 Mon Sep 17 00:00:00 2001
From: "Mekhanoshin, Stanislav"
Date: Wed, 25 Jun 2025 13:27:57 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_pk_f16_fp8` on gfx12
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/145753
>From 5d44b53a20029b6f216bd18f47f49a9e873613e7 Mon Sep 17 00:00:00 2001
From: "Mekhanoshin, Stanislav"
Date: Wed, 25 Jun 2025 13:56:12 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_pk_f16_bf8` on gfx12
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/145747
>From 5e439f780f3eab0a75e68d2bac9c85892c9f34c2 Mon Sep 17 00:00:00 2001
From: "Mekhanoshin, Stanislav"
Date: Wed, 25 Jun 2025 13:27:57 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_pk_f16_fp8` on gfx12
https://github.com/shiltian ready_for_review
https://github.com/llvm/llvm-project/pull/145747
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https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/145747
Co-authored-by: Shilei Tian
>From 86417c4382640e179277338a9040be9b6579dec9 Mon Sep 17 00:00:00 2001
From: "Mekhanoshin, Stanislav"
Date: Wed, 25 Jun 2025 13:27:57 -0400
Subject: [PATCH] [AMDGPU] Add support f
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx1250 -show-mc-encoding -verify-machineinstrs
< %s | FileCheck -check-prefix=GFX1250 %s
shiltian wrote:
I think it is recommended to
@@ -9669,6 +9670,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
+ if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts())
shiltian wrote:
So we want a `0x` instead of a `0x` here? Why is that?
shiltian wrote:
Is this PR part of a stack or something?
https://github.com/llvm/llvm-project/pull/139357
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/141862
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@@ -2627,6 +2629,93 @@ SDValue DAGCombiner::foldSubToAvg(SDNode *N, const SDLoc
&DL) {
return SDValue();
}
+/// Try to fold a pointer arithmetic node.
+/// This needs to be done separately from normal addition, because pointer
+/// addition is not commutative.
+SDValue DAGC
@@ -14935,6 +14936,52 @@ SDValue SITargetLowering::performAddCombine(SDNode *N,
return SDValue();
}
+SDValue SITargetLowering::performPtrAddCombine(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ SelectionDAG &DAG = DCI.DAG;
+ EVT
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/142739
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@@ -2627,6 +2629,93 @@ SDValue DAGCombiner::foldSubToAvg(SDNode *N, const SDLoc
&DL) {
return SDValue();
}
+/// Try to fold a pointer arithmetic node.
+/// This needs to be done separately from normal addition, because pointer
+/// addition is not commutative.
+SDValue DAGC
@@ -14935,6 +14936,52 @@ SDValue SITargetLowering::performAddCombine(SDNode *N,
return SDValue();
}
+SDValue SITargetLowering::performPtrAddCombine(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ SelectionDAG &DAG = DCI.DAG;
+ EVT
@@ -2627,6 +2629,93 @@ SDValue DAGCombiner::foldSubToAvg(SDNode *N, const SDLoc
&DL) {
return SDValue();
}
+/// Try to fold a pointer arithmetic node.
+/// This needs to be done separately from normal addition, because pointer
+/// addition is not commutative.
+SDValue DAGC
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/142777
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/142778
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shiltian wrote:
Is it a "move" or adds new tests? There doesn't seem to be any delete.
https://github.com/llvm/llvm-project/pull/142114
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/141985
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/141804
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@@ -11922,6 +11922,18 @@ bool llvm::isBoolSGPR(SDValue V) {
case ISD::SMULO:
case ISD::UMULO:
return V.getResNo() == 1;
+ case ISD::INTRINSIC_WO_CHAIN: {
+unsigned IntrinsicID = V.getConstantOperandVal(0);
+switch (IntrinsicID) {
+case Intrinsic::amdgcn_is_
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/141589
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@@ -392,6 +394,55 @@ void
AMDGPURegBankCombinerImpl::applyCanonicalizeZextShiftAmt(
MI.eraseFromParent();
}
+bool AMDGPURegBankCombinerImpl::lowerUniformBFX(MachineInstr &MI) const {
+ assert(MI.getOpcode() == TargetOpcode::G_UBFX ||
+ MI.getOpcode() == TargetOpcod
shiltian wrote:
This is still a work in progress, as three test cases are currently crashing.
I'd like to get some early feedback on whether this is the right approach to
support `opsel` for fake16.
https://github.com/llvm/llvm-project/pull/139185
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https://github.com/llvm/llvm-project/pull/139185
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shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/139185?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/139185
None
>From 810682aeeaa305de0a36145770016f7364404908 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 8 May 2025 19:26:31 -0400
Subject: [PATCH] [AMDGPU][Fake16] Support OPSEL for `v_cvt_f16_f32` and
`v_c
https://github.com/shiltian approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/138626
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@@ -1108,47 +1108,25 @@ struct AAAMDWavesPerEU : public AAAMDSizeRangeAttribute
{
Function *F = getAssociatedFunction();
auto &InfoCache = static_cast(A.getInfoCache());
-auto TakeRange = [&](std::pair R) {
- auto [Min, Max] = R;
- ConstantRange Range(AP
@@ -1408,8 +1433,14 @@ static bool runImpl(Module &M, AnalysisGetter &AG,
TargetMachine &TM,
}
}
- ChangeStatus Change = A.run();
- return Change == ChangeStatus::CHANGED;
+ bool Changed = A.run() == ChangeStatus::CHANGED;
shiltian wrote:
I didn't f
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/123995
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@@ -1333,6 +1308,56 @@ static void addPreloadKernArgHint(Function &F,
TargetMachine &TM) {
}
}
+/// The final check and update of the attribute 'amdgpu-waves-per-eu' based on
+/// the determined 'amdgpu-flat-work-group-size' attribute. We can't do this
+/// during attributo
@@ -1108,47 +1108,25 @@ struct AAAMDWavesPerEU : public AAAMDSizeRangeAttribute
{
Function *F = getAssociatedFunction();
auto &InfoCache = static_cast(A.getInfoCache());
-auto TakeRange = [&](std::pair R) {
- auto [Min, Max] = R;
- ConstantRange Range(AP
@@ -1425,8 +1453,14 @@ static bool runImpl(Module &M, AnalysisGetter &AG,
TargetMachine &TM,
}
}
- ChangeStatus Change = A.run();
- return Change == ChangeStatus::CHANGED;
+ bool Changed = A.run() == ChangeStatus::CHANGED;
+
+ if (Changed && (LTOPhase == ThinOrFullL
shiltian wrote:
Will close this for now. I'll revisit this if we can handle the case under
discussion properly.
https://github.com/llvm/llvm-project/pull/137655
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https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/137655
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@@ -11,11 +10,9 @@ define amdgpu_kernel void @ptr_nest_3(ptr addrspace(1)
nocapture readonly %Arg)
; CHECK-NEXT: entry:
; CHECK-NEXT:[[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT:[[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1)
[[ARG:%.
@@ -11,11 +10,9 @@ define amdgpu_kernel void @ptr_nest_3(ptr addrspace(1)
nocapture readonly %Arg)
; CHECK-NEXT: entry:
; CHECK-NEXT:[[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT:[[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1)
[[ARG:%.
https://github.com/shiltian ready_for_review
https://github.com/llvm/llvm-project/pull/137655
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@@ -11,11 +10,9 @@ define amdgpu_kernel void @ptr_nest_3(ptr addrspace(1)
nocapture readonly %Arg)
; CHECK-NEXT: entry:
; CHECK-NEXT:[[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT:[[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1)
[[ARG:%.
shiltian wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/137655?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/137655
None
>From 531195729a62694205763accce085b46d9a5bc10 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 27 Apr 2025 13:38:11 -0400
Subject: [PATCH] [AMDGPU] Remove the pass `AMDGPUPromoteKernelArguments`
--
https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/136865
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https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/136798
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/136304
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 9d2612c4379eb827406642b508f2dce32fc13e59 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 2d75ec2eb1a927513bb92bcb26e313a3831426ef Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 9d2612c4379eb827406642b508f2dce32fc13e59 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 2d75ec2eb1a927513bb92bcb26e313a3831426ef Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 8b975d26cd4540ad95bdaafb02a0f48154cb57f1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 8b975d26cd4540ad95bdaafb02a0f48154cb57f1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
shiltian wrote:
> In the real world, people emit address space 0 allocas all over the place and
> then report backend bugs when it fails in codegen
Technically we can avoid that by just hard error
https://github.com/llvm/llvm-project/pull/136865
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@@ -12603,6 +12603,18 @@ struct AAAddressSpaceImpl : public AAAddressSpace {
auto CheckAddressSpace = [&](Value &Obj) {
if (isa(&Obj))
return true;
+ // Some targets relax the requirement for alloca to be in an exact
address
+ // space, allowing it
shiltian wrote:
> The A field does not assert anything about the content of the module. It does
> not assert that any alloca with a non-A valued alloca can be replaced with an
> A address space alloca. An alloca that does not match this address space is
> not invalid, and you cannot say anythi
shiltian wrote:
> This looks like an attempt to fix up broken IR producers, but I guess that's
> not it?
Yeah, I initially thought that was broken IR too. At first, I was in favor of
not allowing alloca in AS0 at all and just making it a verifier error, like
what was done in
https://github.c
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s -o -
| FileCheck %s
+
+declare void @bar(ptr)
+
+define i32 @static_alloca() {
+; CHECK-LAB
shiltian wrote:
I've updated the PR to use `getAssumedAddrSpace`, which is same as what
`InferAddressSpacePass` does. @arsenm @nikic
https://github.com/llvm/llvm-project/pull/136865
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