@@ -0,0 +1,166 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010
-new-reg-bank-select < %s | FileCheck %s
+
+define amdgpu_ps void @readanylane_to_virtual_vgpr
@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (R
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 7c5c7bf98afe91f015b36e42536a8a700b27b686 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 7c5c7bf98afe91f015b36e42536a8a700b27b686 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145911
>From 046418f7ccd46a2b0c2ea3c9ab15e659de709b27 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (R
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 9cebe6bb5d44a630235a8cce4233e53f68f7bd0c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145911
>From 871140020cf7f3fc5f7fe4cbb657d754ed8ecc2f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145910
>From 7f9708fb95ab169e1c449dbfccbcbdd049518c9e Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:11:48 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add tests for missing readanylane co
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 9cebe6bb5d44a630235a8cce4233e53f68f7bd0c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145911
>From 871140020cf7f3fc5f7fe4cbb657d754ed8ecc2f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145910
>From 7f9708fb95ab169e1c449dbfccbcbdd049518c9e Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:11:48 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add tests for missing readanylane co
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 811ddee3f53fd10f72efa647629d2ab2e34d577b Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
@@ -32,6 +32,7 @@ class RegBankLegalizeHelper {
const MachineUniformityInfo &MUI;
const RegisterBankInfo &RBI;
const RegBankLegalizeRules &RBLRules;
+ const bool IsWave32;
petar-avramovic wrote:
you mean this?
https://github.com/llvm/llvm-project/pull/
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145910
>From 57e9aeccd735186314a9a57bf1142baaf013738f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:11:48 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add tests for missing readanylane co
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145910
>From 57e9aeccd735186314a9a57bf1142baaf013738f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:11:48 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add tests for missing readanylane co
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145911
>From 7c2efb4eae157acba554923fb81f85fd30647f86 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 4c82486cb901855c00a8b6b8de250e96430f9473 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145912
>From 4c82486cb901855c00a8b6b8de250e96430f9473 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 26 Jun 2025 16:03:56 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankle
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/145911
>From 7c2efb4eae157acba554923fb81f85fd30647f86 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
petar-avramovic wrote:
sorry about the noise, graphite was refusing to submit stack. This is latest
version of the patches
https://github.com/llvm/llvm-project/pull/145912
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@@ -115,126 +117,233 @@ class AMDGPURegBankLegalizeCombiner {
VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
- bool isLaneMask(Register Reg) {
-const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
-if (R
https://github.com/petar-avramovic ready_for_review
https://github.com/llvm/llvm-project/pull/145910
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petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145910?utm_source=stack-comment-downstack-mergeability-w
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145911?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic edited
https://github.com/llvm/llvm-project/pull/145911
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petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145912?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/145912
Add rules for G_AMDGPU_BUFFER_LOAD and implement waterfall lowering
for divergent operands that must be sgpr.
>From fc323ccbe1efe163e7644968025cc1c149ad6ca6 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/145911
None
>From ad17135217feeffa0ec343a55768b112f461e8ef Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines i
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/145910
None
>From f88854af08dc7bd943cb222f970d6a41fe441261 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:11:48 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add tests for missing readanyl
https://github.com/petar-avramovic closed
https://github.com/llvm/llvm-project/pull/145887
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petar-avramovic wrote:
https://github.com/llvm/llvm-project/pull/145887
https://github.com/llvm/llvm-project/pull/142790
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petar-avramovic wrote:
https://github.com/llvm/llvm-project/pull/145886
https://github.com/llvm/llvm-project/pull/142789
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petar-avramovic wrote:
https://github.com/llvm/llvm-project/pull/145886
https://github.com/llvm/llvm-project/pull/145885
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petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145887?utm_source=stack-comment-downstack-mergeability-w
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145886?utm_source=stack-comment-downstack-mergeability-w
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145885?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/145887
Add rules for G_AMDGPU_BUFFER_LOAD and implement waterfall lowering
for divergent operands that must be sgpr.
>From ebb36753df2a0df473309eea382c03354a89fbe4 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/145886
None
>From f720d70ecf32314918bfa81f29744f81619ee44e Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines i
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/145885
None
>From fb315fbf12d78a248df12b186e59321fdbfb697a Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:11:48 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add tests for missing readanyl
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142790
>From d5bdc951f61533379fed9a86ed6c0eab18b7893c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:43:04 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankleg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142790
>From d5bdc951f61533379fed9a86ed6c0eab18b7893c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:43:04 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankleg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142789
>From fada12c02954dd1c244c944fa37dbae674284923 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142789
>From fada12c02954dd1c244c944fa37dbae674284923 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142789
>From 28f0f171b27aaf707706db71978d525c12e21491 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
petar-avramovic wrote:
ping
https://github.com/llvm/llvm-project/pull/142790
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https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142790
>From ec14c19baccfeb87380bf99f728b213db3db05e2 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:43:04 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankleg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142790
>From ec14c19baccfeb87380bf99f728b213db3db05e2 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:43:04 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankleg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142789
>From 28f0f171b27aaf707706db71978d525c12e21491 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
@@ -57,6 +57,226 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+bool RegBankLegalizeHelper::executeInWaterfallLoop(
+MachineIRBuilder &B, iterator_range Range,
+SmallSet &SGPROperandRegs) {
+ // Tra
@@ -165,6 +165,8 @@ enum RegBankLLTMappingApplyID {
Sgpr32Trunc,
// Src only modifiers: waterfalls, extends
+ Sgpr32_W,
+ SgprV4S32_W,
petar-avramovic wrote:
Added one above, is it clear now?
https://github.com/llvm/llvm-project/pull/142790
___
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
@@ -137,7 +138,123 @@ class AMDGPURegBankLegalizeCombiner {
return {MatchMI, MatchMI->getOperand(1).getReg()};
}
+ std::tuple tryMatchRALFromUnmerge(Register Src) {
+auto *ReadAnyLane = MRI.getVRegDef(Src);
+if (ReadAnyLane->getOpcode() == AMDGPU::G_AMDGPU_READA
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142790
>From ae9621601118004cc6b363be7fad70092e401cad Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:43:04 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankleg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142790
>From ae9621601118004cc6b363be7fad70092e401cad Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:43:04 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Add waterfall lowering in regbankleg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142789
>From 64d7853a9edefabe8de40748e01348d2d5c017c5 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/142789
>From 64d7853a9edefabe8de40748e01348d2d5c017c5 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 5 Jun 2025 12:17:13 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines in
reg
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/142790
Add rules for G_AMDGPU_BUFFER_LOAD and implement waterfall lowering
for divergent operands that must be sgpr.
>From 6dd26d44b55420f91a1684e78938ea8b426680cc Mon Sep 17 00:00:00 2001
From: Petar Avramovic
https://github.com/petar-avramovic approved this pull request.
https://github.com/llvm/llvm-project/pull/142604
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petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142790?utm_source=stack-comment-downstack-mergeability-w
petar-avramovic wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142789?utm_source=stack-comment-downstack-mergeability-w
https://github.com/petar-avramovic created
https://github.com/llvm/llvm-project/pull/142789
None
>From fcd0dc75f4674297ef1f5c591ecf6c16314ce3e2 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 4 Jun 2025 17:12:16 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Improve readanylane combines i
@@ -2,6 +2,8 @@
# RUN: llc -mtriple=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o
- -regbankselect-fast | FileCheck %s
# RUN: llc -mtriple=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o
- -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdg
petar-avramovic wrote:
This one LGTM, minus patches before
https://github.com/llvm/llvm-project/pull/142602
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petar-avramovic wrote:
Don't like adding all these without use case.
Not sure if we can get away with only checking ptr size and ignoring address
space but in the end it is mostly used for assert.
These are mostly used for loads/stores and atomics, is it really that simple,
all 32bit pointer t
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 50839949c8622e52027d378405d2edc99d9df3a7 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 97161545fc7d53077ec52f9b6abdcc5caf78fff9 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
petar-avramovic wrote:
### Merge activity
* **May 26, 10:03 AM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/132383).
https://github.com/llvm/llvm-project/pull/132383
___
petar-avramovic wrote:
### Merge activity
* **May 26, 10:03 AM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/132385).
https://github.com/llvm/llvm-project/pull/132385
___
petar-avramovic wrote:
### Merge activity
* **May 26, 10:03 AM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/132384).
https://github.com/llvm/llvm-project/pull/132384
___
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 419cfe8adfe34443a380861fe2cfd36400c5fe1f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 4b82d7501c8e754ac36b91924fec89a70046ff63 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:02:27 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 758eec524d2500317583750a75c1885ecbf394af Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 758eec524d2500317583750a75c1885ecbf394af Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 4b82d7501c8e754ac36b91924fec89a70046ff63 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:02:27 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 50839949c8622e52027d378405d2edc99d9df3a7 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From c08c9f0916b724d733ea47e944137e0a8952d365 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:02:27 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From ffc85074898c43ceb52c1ca458bc0fd844e84a60 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 0bc832089bf02e0069f441d70728943de51766c6 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From ffc85074898c43ceb52c1ca458bc0fd844e84a60 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 8 May 2025 12:03:28 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extend
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 0bc832089bf02e0069f441d70728943de51766c6 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Mon, 14 Apr 2025 16:35:19 +0200
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit s
@@ -70,14 +70,29 @@ define i8 @v_ashr_i8_7(i8 %value) {
}
define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) {
-; GCN-LABEL: s_ashr_i8:
-; GCN: ; %bb.0:
-; GCN-NEXT:s_sext_i32_i8 s0, s0
-; GCN-NEXT:s_ashr_i32 s0, s0, s1
-; GCN-NEXT:; return to
@@ -133,6 +133,43 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI,
LLT WideTy,
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ Register Src = MI
@@ -292,13 +311,23 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
case Ext32To64: {
const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg());
MachineInstrBuilder Hi;
-
-if (MI.getOpcode() == AMDGPU::G_ZEXT) {
+switch (MI.getOpcode()) {
+c
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