https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/144699
>From 3240b5d582f6fe5d430f792f0f7d208d80bf7f48 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 18 Jun 2025 13:04:45 +
Subject: [PATCH 1/3] [MLIR][AArch64] Add integration test for lowering
@@ -0,0 +1,336 @@
+// REQUIRES: arm-emulator
+
+// DEFINE: %{compile} = mlir-opt %s \
+// DEFINE: --convert-vector-to-scf --convert-scf-to-cf
--convert-vector-to-llvm='enable-arm-neon enable-arm-i8mm' \
+// DEFINE: --expand-strided-metadata --convert-to-llvm
--finalize-memr
@@ -298,16 +298,139 @@ struct LegalizeSVEMaskLoadConversion : public
OpRewritePattern {
}
};
+/// Transforms a `transfer_read` operation so it reads vector of a type that
+/// can be mapped to an LLVM type. This is done by collapsing trailing
+/// dimensions so we obtain a
@@ -298,16 +298,139 @@ struct LegalizeSVEMaskLoadConversion : public
OpRewritePattern {
}
};
+/// Transforms a `transfer_read` operation so it reads vector of a type that
+/// can be mapped to an LLVM type. This is done by collapsing trailing
+/// dimensions so we obtain a
@@ -0,0 +1,262 @@
+// RUN: mlir-opt --arm-sve-legalize-vector-storage --split-input-file %s |
FileCheck %s
+
+// -
+
+// CHECK-LABEL: @test_base_case
+// CHECK-SAME: %[[I:arg0]]: index, %[[J:arg1]]: index, %[[M:arg2]]:
+// CHECK: %[[COLLAPSE:.+]]
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/143146
>From 198ed819841270aeec7159fe2a9a4c092b8d8af7 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 14 May 2025 09:03:49 +
Subject: [PATCH 1/4] [MLIR] Legalize certain `vector.transfer_read` ops
@@ -298,16 +298,139 @@ struct LegalizeSVEMaskLoadConversion : public
OpRewritePattern {
}
};
+/// Transforms a `transfer_read` operation so it reads vector of a type that
+/// can be mapped to an LLVM type. This is done by collapsing trailing
+/// dimensions so we obtain a
@@ -0,0 +1,262 @@
+// RUN: mlir-opt --arm-sve-legalize-vector-storage --split-input-file %s |
FileCheck %s
+
+// -
+
+// CHECK-LABEL: @test_base_case
+// CHECK-SAME: %[[I:arg0]]: index, %[[J:arg1]]: index, %[[M:arg2]]:
+// CHECK: %[[COLLAPSE:.+]]
@@ -0,0 +1,262 @@
+// RUN: mlir-opt --arm-sve-legalize-vector-storage --split-input-file %s |
FileCheck %s
+
+// -
+
+// CHECK-LABEL: @test_base_case
+// CHECK-SAME: %[[I:arg0]]: index, %[[J:arg1]]: index, %[[M:arg2]]:
+// CHECK: %[[COLLAPSE:.+]]
@@ -0,0 +1,262 @@
+// RUN: mlir-opt --arm-sve-legalize-vector-storage --split-input-file %s |
FileCheck %s
+
+// -
+
+// CHECK-LABEL: @test_base_case
+// CHECK-SAME: %[[I:arg0]]: index, %[[J:arg1]]: index, %[[M:arg2]]:
+// CHECK: %[[COLLAPSE:.+]]
@@ -298,16 +298,139 @@ struct LegalizeSVEMaskLoadConversion : public
OpRewritePattern {
}
};
+/// Transforms a `transfer_read` operation so it reads vector of a type that
+/// can be mapped to an LLVM type. This is done by collapsing trailing
+/// dimensions so we obtain a
@@ -298,16 +298,139 @@ struct LegalizeSVEMaskLoadConversion : public
OpRewritePattern {
}
};
+/// Transforms a `transfer_read` operation so it reads vector of a type that
+/// can be mapped to an LLVM type. This is done by collapsing trailing
+/// dimensions so we obtain a
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From b950757c234900db941ed950ea3469b520d2e28a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/9] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/142422
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/143146
>From 493955781f28b8b6caaeff1b45f7b7a06b43086c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 14 May 2025 09:03:49 +
Subject: [PATCH 1/3] [MLIR] Legalize certain `vector.transfer_read` ops
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/142422
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
momchil-velikov wrote:
Commit message updated.
https://github.com/llvm/llvm-project/pull/142422
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/142422
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From b950757c234900db941ed950ea3469b520d2e28a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/8] [MLIR] Fix incorrect slice contiguity inference in
@@ -83,16 +84,48 @@ func.func @transfer_read_dims_mismatch_contiguous(
return %res : vector<1x1x2x2xi8>
}
-// CHECK-LABEL: func.func @transfer_read_dims_mismatch_contiguous(
+// CHECK-LABEL: func.func @transfer_read_dims_mismatch_contiguous_unit_dims(
// CHECK-SAME:
@@ -630,7 +639,10 @@ class FlattenContiguousRowMajorTransferReadPattern
if (transferReadOp.getMask())
return failure();
-int64_t firstDimToCollapse = sourceType.getRank() - vectorType.getRank();
momchil-velikov wrote:
So, I changed it like this.
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From b950757c234900db941ed950ea3469b520d2e28a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/7] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/143146
>From 6a6d6037b6da51b2da474c99751433542cf35603 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 14 May 2025 09:03:49 +
Subject: [PATCH 1/2] [MLIR] Legalize certain `vector.transfer_read` ops
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From b950757c234900db941ed950ea3469b520d2e28a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/6] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From b950757c234900db941ed950ea3469b520d2e28a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/6] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/143146
>From 6a6d6037b6da51b2da474c99751433542cf35603 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 14 May 2025 09:03:49 +
Subject: [PATCH 1/2] [MLIR] Legalize certain `vector.transfer_read` ops
@@ -49,35 +49,37 @@ FailureOr>
isTranspose2DSlice(vector::TransposeOp op);
/// Return true if `vectorType` is a contiguous slice of `memrefType`.
///
-/// Only the N = vectorType.getRank() trailing dims of `memrefType` are
-/// checked (the other dims are not relevant). Note
@@ -630,7 +639,10 @@ class FlattenContiguousRowMajorTransferReadPattern
if (transferReadOp.getMask())
return failure();
-int64_t firstDimToCollapse = sourceType.getRank() - vectorType.getRank();
momchil-velikov wrote:
> > I've chosen to do maxim
@@ -630,7 +639,10 @@ class FlattenContiguousRowMajorTransferReadPattern
if (transferReadOp.getMask())
return failure();
-int64_t firstDimToCollapse = sourceType.getRank() - vectorType.getRank();
momchil-velikov wrote:
> when might
> lastDyn
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 937afe27b55fb6a61ccef6252eeb33159bca3e99 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/5] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 937afe27b55fb6a61ccef6252eeb33159bca3e99 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/5] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/143146
>From 4d13aa2c48a24e5a76618e78adde41713115f895 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 14 May 2025 09:03:49 +
Subject: [PATCH] [MLIR] Legalize certain `vector.transfer_read` ops of
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/143146
>From 4d13aa2c48a24e5a76618e78adde41713115f895 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 14 May 2025 09:03:49 +
Subject: [PATCH] [MLIR] Legalize certain `vector.transfer_read` ops of
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/143146
THis patch add a transform of `transfer_read` operation to change the vector
type to one that can be mapped to an LLVM type. This is done by collapsing
trailing dimensions so we obtain a vector type wi
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 4c1207b4f72314683eed7d5f8672c6d83db1ef54 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/5] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 4c1207b4f72314683eed7d5f8672c6d83db1ef54 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/5] [MLIR] Fix incorrect slice contiguity inference in
@@ -630,7 +639,10 @@ class FlattenContiguousRowMajorTransferReadPattern
if (transferReadOp.getMask())
return failure();
-int64_t firstDimToCollapse = sourceType.getRank() - vectorType.getRank();
momchil-velikov wrote:
With leading unit dimension
@@ -203,21 +206,21 @@ func.func @transfer_read_dynamic_dim_to_flatten(
return %res : vector<1x2x6xi32>
}
-// CHECK: #[[$MAP:.*]] = affine_map<()[s0, s1] -> (s0 * 24 + s1 * 6)>
+// CHECK: #[[$MAP:.+]] = affine_map<()[s0, s1] -> (s0 * 24 + s1 * 6)>
// CHECK-LABEL: func.func
@@ -582,6 +582,15 @@ static SmallVector getCollapsedIndices(RewriterBase
&rewriter,
namespace {
+/// Helper functon to return the index of the last dynamic dimension in
`shape`.
momchil-velikov wrote:
`std::distance` returns a `ptrdiff_t`, there's a chanc
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 8f9a4002820dcd3de2a5986d53749386a2507eab Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/4] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 8f9a4002820dcd3de2a5986d53749386a2507eab Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/4] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 2eb6c95955dc22b6b59eb4e5ba269e4744bbdd2a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/3] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 2eb6c95955dc22b6b59eb4e5ba269e4744bbdd2a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/3] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/140572
>From 0d2dca54b02ab76d4b847eed764a5284b74fc5f3 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 16 May 2025 15:47:36 +
Subject: [PATCH 1/3] [MLIR] Add
apply_patterns.vector.arm_sve.lower_co
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/140573
>From b5865b5daacc46f53e948bcd6347f4eafc8d2938 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 19 May 2025 14:50:45 +
Subject: [PATCH 1/2] [MLIR] Integration tests for lowering vector.contr
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/140573
>From b5865b5daacc46f53e948bcd6347f4eafc8d2938 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 19 May 2025 14:50:45 +
Subject: [PATCH 1/2] [MLIR] Integration tests for lowering vector.contr
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/140572
>From 0d2dca54b02ab76d4b847eed764a5284b74fc5f3 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 16 May 2025 15:47:36 +
Subject: [PATCH 1/3] [MLIR] Add
apply_patterns.vector.arm_sve.lower_co
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 887f383aa07cca3fe023cd64b3b119cbf013c17b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/3] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 887f383aa07cca3fe023cd64b3b119cbf013c17b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/3] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 1590fe674c00e07171c8842805a06907ed68f242 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/2] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/142422
>From 1590fe674c00e07171c8842805a06907ed68f242 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Jun 2025 15:13:13 +
Subject: [PATCH 1/2] [MLIR] Fix incorrect slice contiguity inference in
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/142422
Previously, slices were sometimes marked as non-contiguous when they were
actually contiguous. This occurred when the vector type had leading unit
dimensions, e.g., `vector<1x1x...x1xd0xd1x...xdn-1xT>`.
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/140573
>From 87f29647c650bdff25f93cef6b1d3ccc63eca63b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 19 May 2025 14:50:45 +
Subject: [PATCH] [MLIR] Integration tests for lowering vector.contract
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/140572
>From df54d59d29e8afc04740e86281bce6be5dd157da Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 16 May 2025 15:47:36 +
Subject: [PATCH 1/2] [MLIR] Add
apply_patterns.vector.arm_sve.lower_co
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/140573
>From 87f29647c650bdff25f93cef6b1d3ccc63eca63b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 19 May 2025 14:50:45 +
Subject: [PATCH] [MLIR] Integration tests for lowering vector.contract
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/140573
None
>From 194c1c7737ea7baa74971666f93312a071f5703d Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 19 May 2025 14:50:45 +
Subject: [PATCH] [MLIR] Integration tests for lowering vector.con
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/140572
None
>From 251f93ea5b87acefac1fbcd6951c3b7870eff83c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 16 May 2025 15:47:36 +
Subject: [PATCH] [MLIR] Add apply_patterns.vector.arm_sve.lower_c
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135636
>From aa8a667f206874af3b26811ec04d58be12ad43de Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 8 Apr 2025 14:43:54 +
Subject: [PATCH 1/3] [MLIR][ArmSVE] Add initial lowering of `vector.cont
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135634
>From e60ca5aadf1043a0cb59d50da5f3dbf68bd50c51 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 10 Apr 2025 14:38:27 +
Subject: [PATCH] [MLIR][ArmSVE] Add an ArmSVE dialect operation which m
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135636
>From aa8a667f206874af3b26811ec04d58be12ad43de Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 8 Apr 2025 14:43:54 +
Subject: [PATCH 1/3] [MLIR][ArmSVE] Add initial lowering of `vector.cont
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135634
>From e60ca5aadf1043a0cb59d50da5f3dbf68bd50c51 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 10 Apr 2025 14:38:27 +
Subject: [PATCH] [MLIR][ArmSVE] Add an ArmSVE dialect operation which m
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135634
>From 528237309c0bfd7bbb51a8fea37b54e07f21ad1d Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 10 Apr 2025 14:38:27 +
Subject: [PATCH] [MLIR][ArmSVE] Add an ArmSVE dialect operation which m
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135636
>From f397467bc167d94a28a919a45c009a8f08b6351b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 8 Apr 2025 14:43:54 +
Subject: [PATCH 1/2] [MLIR][ArmSVE] Add initial lowering of `vector.cont
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135636
>From f397467bc167d94a28a919a45c009a8f08b6351b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 8 Apr 2025 14:43:54 +
Subject: [PATCH 1/2] [MLIR][ArmSVE] Add initial lowering of `vector.cont
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135634
Rate limit ยท GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Aria
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
momchil-velikov wrote:
> One high-level question - would sharing some code between NEON and SVE be
> possible?
No, I can't see it happening and resulting in less, or simpler, or easier to
maintain code.
However, it might be possible to add Neon lowering to this patch and see if
the result is
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135634
>From 5e91c2eb411cba43794fa7db918e88099885849e Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 10 Apr 2025 14:38:27 +
Subject: [PATCH] [MLIR][ArmSVE] Add an ArmSVE dialect operation which m
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135634
>From 5e91c2eb411cba43794fa7db918e88099885849e Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 10 Apr 2025 14:38:27 +
Subject: [PATCH] [MLIR][ArmSVE] Add an ArmSVE dialect operation which m
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135636
>From 8e87a7f3b1438d9542d28c90eb9593ebe8cf6500 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 8 Apr 2025 14:43:54 +
Subject: [PATCH] [MLIR][ArmSVE] Add initial lowering of `vector.contract
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/135636
>From 8e87a7f3b1438d9542d28c90eb9593ebe8cf6500 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 8 Apr 2025 14:43:54 +
Subject: [PATCH] [MLIR][ArmSVE] Add initial lowering of `vector.contract
@@ -273,6 +273,34 @@ def UmmlaOp : ArmSVE_Op<"ummla",
"$acc `,` $src1 `,` $src2 attr-dict `:` type($src1) `to` type($dst)";
}
+def UsmmlaOp : ArmSVE_Op<"usmmla", [Pure,
+AllTypesMatch<["src1", "src2"]>,
+
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/135636
Supersedes https://github.com/llvm/llvm-project/pull/135359
>From 2e61d3ee7b9ac88ae1be8ca248dad1a0880ccff4 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 8 Apr 2025 14:43:54 +
Subject: [P
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/135634
Supersedes https://github.com/llvm/llvm-project/pull/135358
>From 71e2f13ad5922bf93961c5d81fd9d1f5899c80b0 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 10 Apr 2025 14:38:27 +
Subject: [
https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/125066
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/101521
None
>From 3079b62127b9fd2878f9a1bf8ffeb2a5be90ab5b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 1 Aug 2024 17:58:18 +0100
Subject: [PATCH] [AArch64][ARM] Add a release note about _BitInt
https://github.com/momchil-velikov milestoned
https://github.com/llvm/llvm-project/pull/79983
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/79983
None
>From d647f6a4754807648dd11480b3e942571a9e1e25 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 30 Jan 2024 11:13:42 +
Subject: [PATCH] [AArch64] Add some release notes items
---
clan
86 matches
Mail list logo