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https://github.com/llvm/llvm-project/pull/146691
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@@ -96,6 +432,1015 @@ define { <3 x float>, <3 x i32> }
@test_frexp_v3f16_v3i32(<3 x float> %a) {
; CHECK-NEXT:mov v0.16b, v2.16b
; CHECK-NEXT:add sp, sp, #80
; CHECK-NEXT:ret
+;
+; WINDOWS-LABEL: test_frexp_v3f16_v3i32:
+; WINDOWS: .seh_proc test_frexp_v3f16
https://github.com/MacDue updated
https://github.com/llvm/llvm-project/pull/142391
>From 7b0003f249619b6b584d8a6501a2c6048deb1843 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell
Date: Thu, 8 May 2025 17:38:27 +
Subject: [PATCH 1/2] [AArch64] Prepare for split ZPR and PPR area allocation
(N
https://github.com/MacDue updated
https://github.com/llvm/llvm-project/pull/142391
>From 55bd461f342d5dcca49b2bac2f2142be9214823a Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell
Date: Thu, 8 May 2025 17:38:27 +
Subject: [PATCH] [AArch64] Prepare for split ZPR and PPR area allocation
(NFCI)
@@ -3780,25 +3938,49 @@ void AArch64FrameLowering::determineStackHazardSlot(
bool HasFPRCSRs = any_of(SavedRegs.set_bits(), [](unsigned Reg) {
return AArch64::FPR64RegClass.contains(Reg) ||
AArch64::FPR128RegClass.contains(Reg) ||
- AArch64::ZPRRegCla
MacDue wrote:
> If you express the size of the hazard padding between the PPRs and ZPRs as a
> scalable size, that might simplify some of the logic? You wouldn't need to
> represent the two areas as separate stacks, at least.
It would, but for the sizes of hazard padding and vscale we're inter
https://github.com/MacDue commented:
cc @efriedma-quic
https://github.com/llvm/llvm-project/pull/142741
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MacDue wrote:
Rebased this PR stack on the changes from #138609... Which makes things even
hairier :sweat_smile: It would be nice if all these modes were not so
intertwined in the code.
https://github.com/llvm/llvm-project/pull/142392
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https://github.com/MacDue updated
https://github.com/llvm/llvm-project/pull/142391
>From 42af819d001699ae6361d51e34d76a06fe956250 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell
Date: Thu, 8 May 2025 17:38:27 +
Subject: [PATCH] [AArch64] Prepare for split ZPR and PPR area allocation
(NFCI)
MacDue wrote:
> In the implementation you're interested in, is there not a hazard between
> PPRs and GPRs?
There are no hazards between PPRs and GPRs (those types of memory accesses can
both be considered as occurring on the CPU).
> What's the interaction between this and aarch64-enable-zpr-
MacDue wrote:
This is a stacked PR. See previous PRs below:
1. https://github.com/llvm/llvm-project/pull/142390
2. https://github.com/llvm/llvm-project/pull/142391
3. :point_right: https://github.com/llvm/llvm-project/pull/142392
https://github.com/llvm/llvm-project/pull/142392
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https://github.com/llvm/llvm-project/pull/142392
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https://github.com/MacDue ready_for_review
https://github.com/llvm/llvm-project/pull/142391
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MacDue wrote:
This is a stacked PR. Please see the final PR for context.
1. https://github.com/llvm/llvm-project/pull/142390
2. :point_right: https://github.com/llvm/llvm-project/pull/142391
3. https://github.com/llvm/llvm-project/pull/142392
https://github.com/llvm/llvm-project/pull/142391
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https://github.com/llvm/llvm-project/pull/142392
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https://github.com/MacDue created
https://github.com/llvm/llvm-project/pull/142391
This patch attempts to refactor AArch64FrameLowering to allow the size of the
ZPR and PPR areas to be calculated separately. This will be used by a
subsequent patch to support allocating ZPRs and PPRs to separat
MacDue wrote:
Not sure why the bot is asking me (I think it's fine, but I requested the
backport).
cc @arsenm, @RKSimon
https://github.com/llvm/llvm-project/pull/140703
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@@ -4923,9 +4923,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
return Invalid;
break;
case 16:
- if (AccumEVT == MVT::i64)
-Cost *= 2;
- else if (AccumEVT != MVT::i32)
+ if (AccumEVT != MVT::i32)
MacDue w
MacDue wrote:
@sdesmalen-arm What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/137683
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https://github.com/MacDue created
https://github.com/llvm/llvm-project/pull/137683
This cherry-picks https://github.com/llvm/llvm-project/pull/132722 and
https://github.com/llvm/llvm-project/pull/136726 (the latter is based on the
former).
These patches are needed to prevent invalid codegen
@@ -4923,9 +4923,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
return Invalid;
break;
case 16:
- if (AccumEVT == MVT::i64)
-Cost *= 2;
- else if (AccumEVT != MVT::i32)
+ if (AccumEVT != MVT::i32)
MacDue w
https://github.com/MacDue edited
https://github.com/llvm/llvm-project/pull/136173
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@@ -2376,6 +2327,59 @@ class VPReductionRecipe : public VPRecipeWithIRFlags {
}
};
+/// A recipe for forming partial reductions. In the loop, an accumulator and
+/// vector operand are added together and passed to the next iteration as the
+/// next accumulator. After the lo
@@ -253,38 +253,38 @@ define i64 @not_dotp_i8_to_i64_has_neon_dotprod(ptr
readonly %a, ptr readonly %b
; CHECK-MAXBW-SAME: ptr readonly [[A:%.*]], ptr readonly [[B:%.*]])
#[[ATTR1:[0-9]+]] {
; CHECK-MAXBW-NEXT: entry:
; CHECK-MAXBW-NEXT:[[TMP0:%.*]] = call i64 @llvm.vsca
https://github.com/MacDue edited
https://github.com/llvm/llvm-project/pull/126503
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@@ -418,7 +418,13 @@ class LoopVectorizationPlanner {
/// Build VPlans for the specified \p UserVF and \p UserIC if they are
/// non-zero or all applicable candidate VFs otherwise. If vectorization and
/// interleaving should be avoided up-front, no plans are generated.
-
https://github.com/MacDue commented:
A bunch of little comments (mostly just nitpicks from a pass over the PR)
:slightly_smiling_face:
https://github.com/llvm/llvm-project/pull/100579
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@@ -3235,6 +3263,36 @@ void VPWidenPointerInductionRecipe::print(raw_ostream
&O, const Twine &Indent,
}
#endif
+void VPAliasLaneMaskRecipe::execute(VPTransformState &State) {
+ IRBuilderBase Builder = State.Builder;
+ Value *SinkValue = State.get(getSinkValue(), true);
+ V
@@ -3235,6 +3263,36 @@ void VPWidenPointerInductionRecipe::print(raw_ostream
&O, const Twine &Indent,
}
#endif
+void VPAliasLaneMaskRecipe::execute(VPTransformState &State) {
+ IRBuilderBase Builder = State.Builder;
+ Value *SinkValue = State.get(getSinkValue(), true);
+ V
@@ -1331,14 +1356,37 @@ static VPActiveLaneMaskPHIRecipe
*addVPLaneMaskPhiAndUpdateExitBranch(
"index.part.next");
// Create the active lane mask instruction in the VPlan preheader.
- auto *EntryALM =
+ VPValue *Mask =
Builder.createNaryOp(VPInstruction::Acti
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@@ -952,7 +952,6 @@ void VPlan::prepareToExecute(Value *TripCountV, Value
*VectorTripCountV,
IRBuilder<> Builder(State.CFG.PrevBB->getTerminator());
// FIXME: Model VF * UF computation completely in VPlan.
- assert(VFxUF.getNumUsers() && "VFxUF expected to always have us
@@ -1300,14 +1301,38 @@ static VPActiveLaneMaskPHIRecipe
*addVPLaneMaskPhiAndUpdateExitBranch(
cast(CanonicalIVPHI->getBackedgeValue());
// TODO: Check if dropping the flags is needed if
// !DataAndControlFlowWithoutRuntimeCheck.
+ VPValue *IncVal = CanonicalIVIncre
@@ -1416,14 +1466,14 @@ void VPlanTransforms::addActiveLaneMask(
auto *FoundWidenCanonicalIVUser =
find_if(Plan.getCanonicalIV()->users(),
[](VPUser *U) { return isa(U); });
- assert(FoundWidenCanonicalIVUser &&
+ assert(FoundWidenCanonicalIVUser && *Fou
@@ -77,9 +77,13 @@ struct VPlanTransforms {
/// creation) and instead it is handled using active-lane-mask. \p
/// DataAndControlFlowWithoutRuntimeCheck implies \p
/// UseActiveLaneMaskForControlFlow.
+ /// RTChecks refers to the pointer pairs that need aliasing elements
@@ -3073,6 +3075,56 @@ struct VPWidenStoreEVLRecipe final : public
VPWidenMemoryRecipe {
}
};
+// Given a pointer A that is being stored to, and pointer B that is being
+// read from, both with unknown lengths, create a mask that disables
+// elements which could overlap ac
@@ -427,6 +428,29 @@ Value *VPInstruction::generate(VPTransformState &State) {
{PredTy, ScalarTC->getType()},
{VIVElem0, ScalarTC}, nullptr, Name);
}
+ // Count the number of bits set in each lane and redu
@@ -195,6 +195,13 @@ enum class TailFoldingStyle {
DataWithEVL,
};
+enum class RTCheckStyle {
+ /// Branch to scalar loop if checks fails at runtime.
+ ScalarFallback,
+ /// Form a mask based on elements which won't be a WAR or RAW hazard
MacDue wrote:
u
https://github.com/MacDue approved this pull request.
https://github.com/llvm/llvm-project/pull/87976
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https://github.com/MacDue approved this pull request.
https://github.com/llvm/llvm-project/pull/86099
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@@ -316,6 +317,9 @@ class ValueBoundsConstraintSet {
/// Builder for constructing affine expressions.
Builder builder;
+
+ /// The current stop condition function.
+ StopConditionFn stopCondition = nullptr;
MacDue wrote:
Just wondering if this should be
https://github.com/MacDue approved this pull request.
LGTM :+1:
https://github.com/llvm/llvm-project/pull/86098
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