[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

frederik-h wrote: ### Merge activity * **Dec 18, 7:42 AM UTC**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.com/github/pr/llvm/llvm-project/172681). https://github.com/llvm/llvm-project/pull/172681 _

[llvm-branch-commits] [llvm] [RISCV][NFC] Add RISCVVSETVLIInfoAnalysis (PR #172615)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/172615 >From b85f43932660cd181d7358a8ed0f4877640210f6 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Thu, 18 Dec 2025 15:24:52 +0800 Subject: [PATCH] Address comments Created using spr 1.3.6-beta.1 --- llvm/li

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Disable few non useful passes (PR #172796)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Vikram Hegde (vikramRH) Changes Matches the legacy pipeline --- Full diff: https://github.com/llvm/llvm-project/pull/172796.diff 2 Files Affected: - (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+2-2) - (modified)

[llvm-branch-commits] [llvm] [NPM] Update OptimizedRegAlloc and MachineLateOptimization pipelines (PR #172795)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Vikram Hegde (vikramRH) Changes 1. add the StackSlotColoringPass to default pipeline 2. Introduce MachineLateInstrsCleanupPass at the beginning of addMachineLateOptimization (matches the legacy default pipeline) --- Full diff: ht

[llvm-branch-commits] [llvm] [NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline (PR #172794)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Vikram Hegde (vikramRH) Changes Matches the legacy flow. The pass was merged with pre-isel lowering in https://github.com/llvm/llvm-project/pull/97727 --- Full diff: https://github.com/llvm/llvm-project/pull/172794.diff 2 File

[llvm-branch-commits] [llvm] [AMDGPU][NPM] add "addPostBBSections()" to NPM (PR #172793)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Vikram Hegde (vikramRH) Changes --- Patch is 20.58 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/172793.diff 3 Files Affected: - (modified) llvm/include/llvm/Passes/CodeGenPassBui

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Disable few non useful passes (PR #172796)

https://github.com/vikramRH ready_for_review https://github.com/llvm/llvm-project/pull/172796 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline (PR #172794)

https://github.com/vikramRH ready_for_review https://github.com/llvm/llvm-project/pull/172794 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [NPM] Update OptimizedRegAlloc and MachineLateOptimization pipelines (PR #172795)

https://github.com/vikramRH ready_for_review https://github.com/llvm/llvm-project/pull/172795 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][NPM] add "addPostBBSections()" to NPM (PR #172793)

https://github.com/vikramRH ready_for_review https://github.com/llvm/llvm-project/pull/172793 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Disable few non useful passes (PR #172796)

https://github.com/vikramRH edited https://github.com/llvm/llvm-project/pull/172796 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [NPM] Update OptimizedRegAlloc and MachineLateOptimization pipelines (PR #172795)

https://github.com/vikramRH edited https://github.com/llvm/llvm-project/pull/172795 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline (PR #172794)

https://github.com/vikramRH edited https://github.com/llvm/llvm-project/pull/172794 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline (PR #172794)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/172794?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Disable few non useful passes (PR #172796)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/172796?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [NPM] Update OptimizedRegAlloc and MachineLateOptimization pipelines (PR #172795)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/172795?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [AMDGPU][NPM] add "addPostBBSections()" to NPM (PR #172793)

vikramRH wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/172793?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [llvm] [NPM] Update OptimizedRegAlloc and MachineLateOptimization pipelines (PR #172795)

https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/172795 None >From 0744cd90334ebde1eef8e7c12fd96e3e74d0d69d Mon Sep 17 00:00:00 2001 From: vikhegde Date: Wed, 17 Dec 2025 15:17:49 +0530 Subject: [PATCH] [NPM] Update OptimizedRegAlloc and MachineLateOptimization pi

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Disable few non useful passes (PR #172796)

https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/172796 None >From 74c0995f7c2902140accb350a6a2a770292b4aff Mon Sep 17 00:00:00 2001 From: vikhegde Date: Wed, 17 Dec 2025 15:28:47 +0530 Subject: [PATCH] [AMDGPU][NPM] Disable few non useful passes --- llvm/lib/Tar

[llvm-branch-commits] [llvm] [AMDGPU][NPM] add "addPostBBSections()" to NPM (PR #172793)

https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/172793 None >From 3702bd0ff01774a1742b06b7dfe3dbba8ffa22f8 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Wed, 17 Dec 2025 14:51:08 +0530 Subject: [PATCH] [AMDGPU][NPM] add "addPostBBSections()" to NPM --- llvm/incl

[llvm-branch-commits] [llvm] [NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline (PR #172794)

https://github.com/vikramRH created https://github.com/llvm/llvm-project/pull/172794 None >From 0ba5a7a574c6dac59cadad0ad74d46db92a49730 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Wed, 17 Dec 2025 15:00:27 +0530 Subject: [PATCH] [NPM] Remove "LowerConstantIntrinsicsPass" from the pipeline

[llvm-branch-commits] [RISCV][NFC] Add RISCVVSETVLIInfoAnalysis (PR #172615)

@@ -0,0 +1,605 @@ +//===- RISCVInsertVSETVLI.cpp - Insert VSETVLI instructions ---===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[llvm-branch-commits] [RISCV][NFC] Add RISCVVSETVLIInfoAnalysis (PR #172615)

@@ -0,0 +1,516 @@ +//===- RISCVInsertVSETVLI.cpp - Insert VSETVLI instructions ---===// topperc wrote: Header comments need to be updated. https://github.com/llvm/llvm-project/pull/172615 ___ llvm-branch-c

[llvm-branch-commits] [RISCV][NFC] Add RISCVVSETVLIInfoAnalysis (PR #172615)

@@ -0,0 +1,605 @@ +//===- RISCVInsertVSETVLI.cpp - Insert VSETVLI instructions ---===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[llvm-branch-commits] [RISCV][NFC] Add RISCVVSETVLIInfoAnalysis (PR #172615)

@@ -0,0 +1,605 @@ +//===- RISCVInsertVSETVLI.cpp - Insert VSETVLI instructions ---===// topperc wrote: Header comment needs to be updated https://github.com/llvm/llvm-project/pull/172615 ___ llvm-branch-co

[llvm-branch-commits] [flang] 1bee351 - Revert "[flang][cuda] Add support for derived-type initialization on device (…"

Author: Valentin Clement (バレンタイン クレメン) Date: 2025-12-17T12:56:17-08:00 New Revision: 1bee3518991208fad0e1998f71e0a82f7f449f7a URL: https://github.com/llvm/llvm-project/commit/1bee3518991208fad0e1998f71e0a82f7f449f7a DIFF: https://github.com/llvm/llvm-project/commit/1bee3518991208fad0e1998f71e0a

[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

https://github.com/arsenm approved this pull request. Maybe should use the work legalize instead of expand but I suppose atomic is already atomic expand https://github.com/llvm/llvm-project/pull/172681 ___ llvm-branch-commits mailing list llvm-branch

[llvm-branch-commits] [clang] [Clang] Add __builtin_allow_sanitize_check() (PR #172030)

@@ -0,0 +1,24 @@ +// RUN: %clang_cc1 -fsyntax-only -verify %s + +void test_builtin_allow_sanitize_check() { + // Test with non-string literal argument melver wrote: Done. https://github.com/llvm/llvm-project/pull/172030 _

[llvm-branch-commits] [clang] [Clang] Add __builtin_allow_sanitize_check() (PR #172030)

@@ -3549,6 +3549,38 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, llvm::MetadataAsValue::get(Ctx, llvm::MDString::get(Ctx, Kind))); return RValue::get(Allow); } + case Builtin::BI__builtin_allow_sanitize_check: { +Intrin

[llvm-branch-commits] [clang] [Clang] Add __builtin_allow_sanitize_check() (PR #172030)

https://github.com/melver updated https://github.com/llvm/llvm-project/pull/172030 >From d4f149dbb21fd7f5e706560b1aa3b8f0b9fa5ae9 Mon Sep 17 00:00:00 2001 From: Marco Elver Date: Fri, 12 Dec 2025 17:18:15 +0100 Subject: [PATCH 1/2] tweak test Created using spr 1.3.8-beta.1 --- clang/test/Code

[llvm-branch-commits] [mlir] 82e282f - Revert "[mlir][math] Add FP software implementation lowering pass: math-to-ap…"

Author: Maksim Levental Date: 2025-12-17T10:52:04-08:00 New Revision: 82e282f7643d79c830e8288d15b72ef55a093fe1 URL: https://github.com/llvm/llvm-project/commit/82e282f7643d79c830e8288d15b72ef55a093fe1 DIFF: https://github.com/llvm/llvm-project/commit/82e282f7643d79c830e8288d15b72ef55a093fe1.dif

[llvm-branch-commits] [clang] [llvm] [PowerPC] Add support for AMO store builtins (PR #170933)

@@ -11482,6 +11482,30 @@ SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op, return DAG.getStore(DAG.getEntryNode(), DL, Op.getOperand(ArgStart + 2), Op.getOperand(ArgStart + 1), MachinePointerInfo()); } + case Intrinsic::ppc_amo_stwat: +

[llvm-branch-commits] [clang] [llvm] [PowerPC] Add support for AMO store builtins (PR #170933)

@@ -11482,6 +11482,30 @@ SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op, return DAG.getStore(DAG.getEntryNode(), DL, Op.getOperand(ArgStart + 2), Op.getOperand(ArgStart + 1), MachinePointerInfo()); } + case Intrinsic::ppc_amo_stwat: +

[llvm-branch-commits] [llvm] AMDGPU: Add pattern for copysign of 0 (PR #172699)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/172699?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] AMDGPU: Add pattern for copysign of 0 (PR #172699)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/172699 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_V4COMPAT` (PR #172646)

https://github.com/michaelrj-google approved this pull request. LGTM, please add a short description of what this function is to the commit description https://github.com/llvm/llvm-project/pull/172646 ___ llvm-branch-commits mailing list llvm-branch-c

[llvm-branch-commits] [llvm] AMDGPU: Add pattern for copysign of 0 (PR #172699)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) Changes Avoiding v_bfi_b32 is desirable since on gfx9 it requires materializing the constant. Similar could be done for infinity, with or 0x7fff --- Patch is 157.86 KiB, truncated to 20.00 KiB below,

[llvm-branch-commits] [clang] [flang] [llvm] [openmp] [Flang] Move builtin .mod generation into runtimes (Reapply #137828) (PR #171515)

vzakhari wrote: Hi Michael, do you have an approximate ETA for this merge? I see you are making more changes, so I am just wondering if you think they will keep coming or you are close to the finish. https://github.com/llvm/llvm-project/pull/171515 _

[llvm-branch-commits] [clang] 06f36bc - Revert "Revert "Reland [clang][modules-driver] Add scanner to detect C++20 mo…"

Author: Naveen Seth Hanig Date: 2025-12-17T22:17:36+05:30 New Revision: 06f36bc97d7d195ddc847270c2f5ba055408433d URL: https://github.com/llvm/llvm-project/commit/06f36bc97d7d195ddc847270c2f5ba055408433d DIFF: https://github.com/llvm/llvm-project/commit/06f36bc97d7d195ddc847270c2f5ba055408433d.d

[llvm-branch-commits] [clang] [flang] [llvm] [openmp] [Flang] Move builtin .mod generation into runtimes (Reapply #137828) (PR #171515)

https://github.com/Meinersbur edited https://github.com/llvm/llvm-project/pull/171515 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-backend-m68k Author: Frederik Harwath (frederik-h) Changes The pass now contains a non-fp expansion and should be used for any similar expansions regardless of the types involved. Hence a generic name seems apt. Renam

[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

llvmbot wrote: @llvm/pr-subscribers-backend-loongarch Author: Frederik Harwath (frederik-h) Changes The pass now contains a non-fp expansion and should be used for any similar expansions regardless of the types involved. Hence a generic name seems apt. Rename the source files, pass, and a

[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

llvmbot wrote: @llvm/pr-subscribers-backend-arm Author: Frederik Harwath (frederik-h) Changes The pass now contains a non-fp expansion and should be used for any similar expansions regardless of the types involved. Hence a generic name seems apt. Rename the source files, pass, and adjust

[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

https://github.com/frederik-h ready_for_review https://github.com/llvm/llvm-project/pull/172681 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

https://github.com/frederik-h updated https://github.com/llvm/llvm-project/pull/172681 >From d4d2a8cf2e3a1789584de25f17a27a03df159fca Mon Sep 17 00:00:00 2001 From: Frederik Harwath Date: Wed, 17 Dec 2025 08:57:12 -0500 Subject: [PATCH] [CodeGen] Rename expand-fp to expand-ir-insts The pass no

[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/include/llvm/CodeGen/Passes.h llvm/includ

[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

https://github.com/frederik-h updated https://github.com/llvm/llvm-project/pull/172681 >From 0304d78b5c48858ce09addc8dd8f713c46ff93bc Mon Sep 17 00:00:00 2001 From: Frederik Harwath Date: Wed, 17 Dec 2025 08:57:12 -0500 Subject: [PATCH] [CodeGen] Rename expand-fp to expand-ir-insts The pass no

[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

frederik-h wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/172681?utm_source=stack-comment-downstack-mergeability-warnin

[llvm-branch-commits] [llvm] [CodeGen] Rename expand-fp to expand-ir-insts (PR #172681)

https://github.com/frederik-h created https://github.com/llvm/llvm-project/pull/172681 The pass now contains a non-fp expansion and should be used for any similar expansions regardless of the types involved. Hence a generic name seems apt. Rename the source files, pass, and adjust the pass desc

[llvm-branch-commits] [llvm] AMDGPU: Handle amdgcn_rcp in computeKnownFPClass (PR #172490)

@@ -5553,6 +5553,39 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, // TODO: Copy inf handling from instructions break; +case Intrinsic::amdgcn_rcp: { + KnownFPClass KnownSrc; + computeKnownFPClass(II->getArgOperand(0), Demande

[llvm-branch-commits] [llvm] AMDGPU: Handle amdgcn_rcp in computeKnownFPClass (PR #172490)

@@ -5553,6 +5553,39 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, // TODO: Copy inf handling from instructions break; +case Intrinsic::amdgcn_rcp: { + KnownFPClass KnownSrc; + computeKnownFPClass(II->getArgOperand(0), Demande

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_V4COMPAT` (PR #172646)

llvmbot wrote: @llvm/pr-subscribers-libc Author: Connector Switch (c8ef) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/172646.diff 2 Files Affected: - (modified) libc/include/llvm-libc-macros/netinet-in-macros.h (+6) - (modified) libc/test/include/netinet_in_test.c

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_V4COMPAT` (PR #172646)

https://github.com/c8ef ready_for_review https://github.com/llvm/llvm-project/pull/172646 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] ValueTracking: Handle amdgcn_exp2 in computeKnownFPClass (PR #172495)

@@ -5374,7 +5374,8 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, } case Intrinsic::exp: case Intrinsic::exp2: -case Intrinsic::exp10: { +case Intrinsic::exp10: +case Intrinsic::amdgcn_exp2: { Known.knownNot(fcNegative);

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_V4COMPAT` (PR #172646)

c8ef wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/172646?utm_source=stack-comment-downstack-mergeability-warning"; >

[llvm-branch-commits] [llvm] ValueTracking: Handle amdgcn_log in computeKnownFPClass (PR #172492)

jayfoad wrote: ```suggestion if ((InterestedClasses & (fcNan | fcInf | fcSubnormal)) == fcNone) ``` https://github.com/llvm/llvm-project/pull/172492 ___ llvm-branch-commits mailing list llvm-branch-commits@lists

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_V4COMPAT` (PR #172646)

https://github.com/c8ef created https://github.com/llvm/llvm-project/pull/172646 None >From 886d2a0d7bbc21173a6731de0d6bea04d612b050 Mon Sep 17 00:00:00 2001 From: c8ef Date: Wed, 17 Dec 2025 20:57:20 +0800 Subject: [PATCH] [libc] Add `IN6_IS_ADDR_V4COMPAT` --- libc/include/llvm-libc-macros/n

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_V4MAPPED` (PR #172645)

llvmbot wrote: @llvm/pr-subscribers-libc Author: Connector Switch (c8ef) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/172645.diff 2 Files Affected: - (modified) libc/include/llvm-libc-macros/netinet-in-macros.h (+8) - (modified) libc/test/include/netinet_in_test.c

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_V4MAPPED` (PR #172645)

https://github.com/c8ef ready_for_review https://github.com/llvm/llvm-project/pull/172645 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_V4MAPPED` (PR #172645)

c8ef wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/172645?utm_source=stack-comment-downstack-mergeability-warning"; >

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_V4MAPPED` (PR #172645)

https://github.com/c8ef created https://github.com/llvm/llvm-project/pull/172645 None >From 0a03867534b22394304030c6f933781b8bb60ea8 Mon Sep 17 00:00:00 2001 From: c8ef Date: Wed, 17 Dec 2025 20:47:11 +0800 Subject: [PATCH] [libc] Add `IN6_IS_ADDR_V4MAPPED` --- libc/include/llvm-libc-macros/n

[llvm-branch-commits] [llvm] ValueTracking: Handle amdgcn_exp2 in computeKnownFPClass (PR #172495)

https://github.com/dtcxzyw approved this pull request. https://github.com/llvm/llvm-project/pull/172495 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_MC*` (PR #172643)

llvmbot wrote: @llvm/pr-subscribers-libc Author: Connector Switch (c8ef) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/172643.diff 2 Files Affected: - (modified) libc/include/llvm-libc-macros/netinet-in-macros.h (+20) - (modified) libc/test/include/netinet_in_test.

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_MC*` (PR #172643)

c8ef wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.com/github/pr/llvm/llvm-project/172643?utm_source=stack-comment-downstack-mergeability-warning"; >

[llvm-branch-commits] [llvm] ValueTracking: Handle amdgcn_log in computeKnownFPClass (PR #172492)

https://github.com/dtcxzyw approved this pull request. https://github.com/llvm/llvm-project/pull/172492 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_MC*` (PR #172643)

https://github.com/c8ef ready_for_review https://github.com/llvm/llvm-project/pull/172643 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [libc] [libc] Add `IN6_IS_ADDR_MC*` (PR #172643)

https://github.com/c8ef created https://github.com/llvm/llvm-project/pull/172643 None >From 27557d0d8ab2d9e3bb6c6e2a97160f6e60eb513a Mon Sep 17 00:00:00 2001 From: c8ef Date: Wed, 17 Dec 2025 20:32:55 +0800 Subject: [PATCH] [libc] Add `IN6_IS_ADDR_MC*` --- .../llvm-libc-macros/netinet-in-macr

[llvm-branch-commits] [lld] [lld][LoongArch] Add reloc types for LA32R/LA32S (PR #172618)

github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff origin/main HEAD --extensions h,cpp -- lld/ELF/Arch/LoongArch.cpp lld/ELF/InputSectio

[llvm-branch-commits] [clang] [llvm] [clang][LoongArch] Add support for LoongArch32 (PR #172619)

llvmbot wrote: @llvm/pr-subscribers-backend-loongarch Author: hev (heiher) Changes This patch adds support for LoongArch32, as introduced in la-toolchain-conventions v1.2. Link: https://github.com/loongson/la-toolchain-conventions/releases/tag/releases%2Fv1.2 Link: https://gcc.gnu.org/p

[llvm-branch-commits] [clang] [llvm] [clang][LoongArch] Add support for LoongArch32 (PR #172619)

llvmbot wrote: @llvm/pr-subscribers-clang-driver Author: hev (heiher) Changes This patch adds support for LoongArch32, as introduced in la-toolchain-conventions v1.2. Link: https://github.com/loongson/la-toolchain-conventions/releases/tag/releases%2Fv1.2 Link: https://gcc.gnu.org/piperm

[llvm-branch-commits] [clang] [llvm] [clang][LoongArch] Add support for LoongArch32 (PR #172619)

https://github.com/heiher created https://github.com/llvm/llvm-project/pull/172619 This patch adds support for LoongArch32, as introduced in la-toolchain-conventions v1.2. Link: https://github.com/loongson/la-toolchain-conventions/releases/tag/releases%2Fv1.2 Link: https://gcc.gnu.org/piperma

[llvm-branch-commits] [lld] [lld][LoongArch] Add reloc types for LA32R/LA32S (PR #172618)

llvmbot wrote: @llvm/pr-subscribers-lld-elf Author: hev (heiher) Changes This patch adds support for processing the relocation types introduced in la-abi-specs v2.50. Link: https://github.com/loongson/la-abi-specs/pull/16 Link: https://sourceware.org/pipermail/binutils/2025-December/1460

[llvm-branch-commits] [lld] [lld][LoongArch] Add reloc types for LA32R/LA32S (PR #172618)

https://github.com/heiher created https://github.com/llvm/llvm-project/pull/172618 This patch adds support for processing the relocation types introduced in la-abi-specs v2.50. Link: https://github.com/loongson/la-abi-specs/pull/16 Link: https://sourceware.org/pipermail/binutils/2025-December/

[llvm-branch-commits] [RISCV][NFC] Add RISCVVSETVLIInfoAnalysis (PR #172615)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/172615 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV][NFC] Add RISCVVSETVLIInfoAnalysis (PR #172615)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/172615 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV][NFC] Add RISCVVSETVLIInfoAnalysis (PR #172615)

llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: Pengcheng Wang (wangpc-pp) Changes --- Patch is 81.69 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/172615.diff 6 Files Affected: - (modified) llvm/lib/Target/RISCV/CMakeLists.txt

[llvm-branch-commits] [llvm] [RISCV] Schedule RVV instructions with compatible type first (PR #95924)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/95924 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Schedule RVV instructions with compatible type first (PR #95924)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/95924 >From 5ac4ff3040f8a5a6cc68efffe3349ef9d181ddec Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 18 Jun 2024 21:33:25 +0800 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =

[llvm-branch-commits] [RISCV][NFC] Add RISCVVSETVLIInfoAnalysis (PR #172615)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/172615 None ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits