@@ -465,23 +473,25 @@ void MachineSMEABI::emitAllocateLazySaveBuffer(
auto &Subtarget = MF.getSubtarget();
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
+ auto *AFI = MF.getInfo();
DebugLoc DL = getDebugLoc(MBB,
https://github.com/MacDue updated
https://github.com/llvm/llvm-project/pull/149063
>From 4250bec812603b7520dc36f26d68a2c3834ad6cd Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell
Date: Tue, 15 Jul 2025 11:47:39 +
Subject: [PATCH 1/2] [AArch64][SME] Support Windows/stack probes in
MachineSME
https://github.com/MacDue updated
https://github.com/llvm/llvm-project/pull/149510
>From c2d34149b2860cadf03824cc35a724775aaf60f8 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell
Date: Tue, 15 Jul 2025 17:00:04 +
Subject: [PATCH] [AArch64][SME] Propagate desired ZA states in the
MachineSMEA
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp --
llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
```
https://github.com/MacDue created
https://github.com/llvm/llvm-project/pull/149510
This patch adds a propagation step to the MachineSMEABIPass that propagates
desired ZA states forwards (from predecessors to successors).
The aim of this is to pick better ZA states for edge bundles, as when man
@@ -4007,7 +4007,8 @@ SDValue
AMDGPUTargetLowering::performIntrinsicWOChainCombine(
case Intrinsic::amdgcn_rcp_legacy:
case Intrinsic::amdgcn_rsq_legacy:
case Intrinsic::amdgcn_rsq_clamp:
- case Intrinsic::amdgcn_tanh: {
+ case Intrinsic::amdgcn_tanh:
+ case Intrinsic
@@ -828,9 +869,49 @@ void runLifetimeSafetyAnalysis(const DeclContext &DC,
const CFG &Cfg,
///blocks; only Decls are visible. Therefore, loans in a block that
///never reach an Origin associated with a Decl can be safely dropped by
///the analysis.
- Lifeti
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/149158
>From e6fc855297a7f20616b00d3e0e0ad12d89463a49 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Wed, 16 Jul 2025 18:22:39 +
Subject: [PATCH] address comment
---
.../clang/Analysis/Analyses/LifetimeSafety.
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/148712
>From 8c5c8f1e38bfdcc5788caa3d47100cac83fa016f Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Mon, 14 Jul 2025 19:37:49 +
Subject: [PATCH] [LifetimeSafety] Add loan expiry analysis
---
.../clang/Analysi
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/148712
>From 8c5c8f1e38bfdcc5788caa3d47100cac83fa016f Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Mon, 14 Jul 2025 19:37:49 +
Subject: [PATCH] [LifetimeSafety] Add loan expiry analysis
---
.../clang/Analysi
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/148976
>From b591be301aa71b31b064a101aae84236a5f715a7 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Tue, 15 Jul 2025 22:19:48 +
Subject: [PATCH] add-liveness-finally
---
.../clang/Analysis/Analyses/LifetimeSa
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/148976
>From b591be301aa71b31b064a101aae84236a5f715a7 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Tue, 15 Jul 2025 22:19:48 +
Subject: [PATCH] add-liveness-finally
---
.../clang/Analysis/Analyses/LifetimeSa
@@ -0,0 +1,46 @@
+; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s
arsenm wrote:
```suggestion
; RUN: not llvm-as -disable-output %s 2>&1 | FileCheck %s
```
https://github.com/llvm/llvm-project/pull/145859
___
ll
@@ -7997,6 +7997,43 @@ void SelectionDAGBuilder::visitIntrinsicCall(const
CallInst &I,
HasTailCall = true;
return;
}
+ case Intrinsic::amdgcn_call_whole_wave: {
+TargetLowering::ArgListTy Args;
+
+// The first argument is the callee. Skip it when assembling
https://github.com/gysit approved this pull request.
Happy to take the role.
https://github.com/llvm/llvm-project/pull/149487
___
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https://github.com/rengolin approved this pull request.
https://github.com/llvm/llvm-project/pull/149488
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ftynse wrote:
@jpienaar @rengolin @banach-space please approve to indicate that you agree to
take on the role.
@llvm/project-council FYI
https://github.com/llvm/llvm-project/pull/149488
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llvmbot wrote:
@llvm/pr-subscribers-mlir
Author: Oleksandr "Alex" Zinenko (ftynse)
Changes
This is a nomination for the maintainers of the tensor compiler category within
MLIR as proposed in
https://discourse.llvm.org/t/mlir-project-maintainers/87189. As agreed in the
Project Council mee
https://github.com/ftynse created
https://github.com/llvm/llvm-project/pull/149488
This is a nomination for the maintainers of the tensor compiler category within
MLIR as proposed in
https://discourse.llvm.org/t/mlir-project-maintainers/87189. As agreed in the
Project Council meeting on July 1
llvmbot wrote:
@llvm/pr-subscribers-mlir
Author: Oleksandr "Alex" Zinenko (ftynse)
Changes
This is a nomination for the maintainers of the egress category within MLIR as
proposed in
https://discourse.llvm.org/t/mlir-project-maintainers/87189. As agreed in the
Project Council meeting on J
ftynse wrote:
@matthias-springer @gysit @banach-space please approve to indicate that you
agree to take on the role.
@llvm/project-council FYI
https://github.com/llvm/llvm-project/pull/149487
___
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llvm-branch-commits@l
https://github.com/ftynse created
https://github.com/llvm/llvm-project/pull/149487
This is a nomination for the maintainers of the egress category within MLIR as
proposed in
https://discourse.llvm.org/t/mlir-project-maintainers/87189. As agreed in the
Project Council meeting on July 17, we are
llvmbot wrote:
@llvm/pr-subscribers-backend-loongarch
Author: ZhaoQi (zhaoqi5)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/149486.diff
8 Files Affected:
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+3-2)
- (modified) llvm/test/CodeGen/LoongAr
https://github.com/zhaoqi5 created
https://github.com/llvm/llvm-project/pull/149486
None
>From 57e55fb8e9c3f5b31edf66cb19e18ff98954aacf Mon Sep 17 00:00:00 2001
From: Qi Zhao
Date: Fri, 18 Jul 2025 17:41:27 +0800
Subject: [PATCH] [LoongArch] Optimize general fp build_vector lowering
---
.../
@@ -828,9 +869,49 @@ void runLifetimeSafetyAnalysis(const DeclContext &DC,
const CFG &Cfg,
///blocks; only Decls are visible. Therefore, loans in a block that
///never reach an Origin associated with a Decl can be safely dropped by
///the analysis.
- Lifeti
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145329
>From f6b9cec969f3c9a786f2215dc79a7c0713ada2cb Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 03:51:19 -0400
Subject: [PATCH] [AMDGPU][SDAG] Test ISD::PTRADD handling in various special
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146074
>From 4a0dcfa906065b4028af4ef9a9fe50674fcf88d4 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 26 Jun 2025 06:10:35 -0400
Subject: [PATCH] [SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD
tran
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145330
>From 42d07f1bfe5db29a746c4bd9d2dc4cfdcc106497 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 04:03:53 -0400
Subject: [PATCH 1/2] [AMDGPU][SDAG] Handle ISD::PTRADD in various special
cas
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From 8a75455c276df97d56a56de5c0444b57ff6b6561 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default
A
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145330
>From 42d07f1bfe5db29a746c4bd9d2dc4cfdcc106497 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 04:03:53 -0400
Subject: [PATCH 1/2] [AMDGPU][SDAG] Handle ISD::PTRADD in various special
cas
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 1d93ad2c4998fb9d400946e03c5176ca82fad6d9 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/3] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we ca
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From 8a75455c276df97d56a56de5c0444b57ff6b6561 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default
A
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 1d93ad2c4998fb9d400946e03c5176ca82fad6d9 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/3] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we ca
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146074
>From 4a0dcfa906065b4028af4ef9a9fe50674fcf88d4 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 26 Jun 2025 06:10:35 -0400
Subject: [PATCH] [SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD
tran
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145329
>From f6b9cec969f3c9a786f2215dc79a7c0713ada2cb Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 03:51:19 -0400
Subject: [PATCH] [AMDGPU][SDAG] Test ISD::PTRADD handling in various special
https://github.com/aengelke edited
https://github.com/llvm/llvm-project/pull/149465
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@@ -433,42 +434,44 @@ static void writeFragment(raw_ostream &OS, const
MCAssembler &Asm,
const auto &EF = cast(F);
OS << StringRef(EF.getContents().data(), EF.getContents().size());
OS << StringRef(EF.getVarContents().data(), EF.getVarContents().size());
-if (F
https://github.com/aengelke commented:
I like reducing the number of hooks, but the const_cast feels to hacky.
https://github.com/llvm/llvm-project/pull/149465
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@@ -230,22 +230,24 @@ uint64_t MCAssembler::computeFragmentSize(const
MCFragment &F) const {
case MCFragment::FT_Align: {
unsigned Offset = F.Offset + F.getFixedSize();
unsigned Size = offsetToAlignment(Offset, F.getAlignment());
-
-// Insert extra Nops for code
OCHyams wrote:
As for the pre-merge on this one: the abi-compare bot thing seems cool, though
I don't think the reported failure is for this patch, I've not touched any
function signatures here
https://github.com/llvm/llvm-project/pull/149053
___
llv
@@ -2857,15 +2857,26 @@ tryToMatchAndCreateExtendedReduction(VPReductionRecipe
*Red, VPCostContext &Ctx,
VPValue *VecOp = Red->getVecOp();
// Clamp the range if using extended-reduction is profitable.
- auto IsExtendedRedValidAndClampRange = [&](unsigned Opcode, bool isZ
@@ -2955,12 +2966,14 @@
tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
// Match reduce.add(mul(ext, ext)).
if (RecipeA && RecipeB &&
-(RecipeA->getOpcode() == RecipeB->getOpcode() || A == B) &&
+(RecipeA->getOpcode() == RecipeB->getO
@@ -2678,6 +2684,23 @@ InstructionCost
VPExpressionRecipe::computeCost(ElementCount VF,
case ExpressionTypes::ExtNegatedMulAccReduction:
case ExpressionTypes::ExtMulAccReduction: {
bool Negated = ExpressionType ==
ExpressionTypes::ExtNegatedMulAccReduction;
+if (i
@@ -2532,7 +2533,10 @@ class VPPartialReductionRecipe : public
VPReductionRecipe {
Opcode(Opcode), VFScaleFactor(ScaleFactor) {
[[maybe_unused]] auto *AccumulatorRecipe =
getChainOp()->getDefiningRecipe();
-assert((isa(AccumulatorRecipe) ||
+// When
@@ -2470,7 +2470,8 @@ class VPReductionRecipe : public VPRecipeWithIRFlags {
static inline bool classof(const VPRecipeBase *R) {
return R->getVPDefID() == VPRecipeBase::VPReductionSC ||
- R->getVPDefID() == VPRecipeBase::VPReductionEVLSC;
+ R->getVPDe
https://github.com/NickGuy-Arm approved this pull request.
https://github.com/llvm/llvm-project/pull/147302
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@@ -2955,12 +2966,14 @@
tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
// Match reduce.add(mul(ext, ext)).
if (RecipeA && RecipeB &&
-(RecipeA->getOpcode() == RecipeB->getOpcode() || A == B) &&
+(RecipeA->getOpcode() == RecipeB->getO
https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/149197
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@@ -5193,6 +5194,34 @@ void Verifier::visitCallsiteMetadata(Instruction &I,
MDNode *MD) {
visitCallStackMetadata(MD);
}
+static inline bool isConstantIntMetadataOperand(const Metadata *MD) {
+ if (auto *VAL = dyn_cast(MD)) {
nikic wrote:
No braces for sin
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146076
>From 629fb4549d552b8ba919c1b75cc8274038b0192c Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 05:38:52 -0400
Subject: [PATCH] [AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default
A
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146075
>From 6f98b3a7b6207c50e13d1a549e2098d93875be7b Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 27 Jun 2025 04:23:50 -0400
Subject: [PATCH 1/3] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR
If we ca
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/146074
>From 293652f82cf41da5df1ad9df53df7a5d562dbd09 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Thu, 26 Jun 2025 06:10:35 -0400
Subject: [PATCH] [SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD
tran
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145330
>From a6bee3e460ef6b51948ab4eedbcb211d8b625a2e Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 04:03:53 -0400
Subject: [PATCH 1/2] [AMDGPU][SDAG] Handle ISD::PTRADD in various special
cas
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145329
>From cbc611c9e083626fc76d66b4351822097c6aa3b1 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 03:51:19 -0400
Subject: [PATCH] [AMDGPU][SDAG] Test ISD::PTRADD handling in various special
ritter-x2a wrote:
### Merge activity
* **Jul 18, 7:54 AM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/143880).
https://github.com/llvm/llvm-project/pull/143880
_
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/148115
>From 507b21daecf165a7293766b3cd61734e87e53ae8 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Thu, 10 Jul 2025 18:53:39 +0530
Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it
---
llvm/include
https://github.com/vikramRH updated
https://github.com/llvm/llvm-project/pull/148115
>From 507b21daecf165a7293766b3cd61734e87e53ae8 Mon Sep 17 00:00:00 2001
From: vikhegde
Date: Thu, 10 Jul 2025 18:53:39 +0530
Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it
---
llvm/include
@@ -828,9 +869,49 @@ void runLifetimeSafetyAnalysis(const DeclContext &DC,
const CFG &Cfg,
///blocks; only Decls are visible. Therefore, loans in a block that
///never reach an Origin associated with a Decl can be safely dropped by
///the analysis.
- Lifeti
MaskRay wrote:
I haven't had the chance to review this patch in detail, but I’m concerned
about the number of linker options required for the CFI feature. While I
recognize its benefits, the complexity seems excessive.
https://github.com/llvm/llvm-project/pull/149448
__
llvmbot wrote:
@llvm/pr-subscribers-mc
@llvm/pr-subscribers-backend-risc-v
Author: Fangrui Song (MaskRay)
Changes
Previously, two MCAsmBackend hooks were used, with
shouldInsertFixupForCodeAlign calling getWriter().recordRelocation
directly, bypassing generic code.
This patch:
* Introduc
llvmbot wrote:
@llvm/pr-subscribers-backend-loongarch
Author: Fangrui Song (MaskRay)
Changes
Previously, two MCAsmBackend hooks were used, with
shouldInsertFixupForCodeAlign calling getWriter().recordRelocation
directly, bypassing generic code.
This patch:
* Introduces MCAsmBackend::rela
https://github.com/MaskRay created
https://github.com/llvm/llvm-project/pull/149465
Previously, two MCAsmBackend hooks were used, with
shouldInsertFixupForCodeAlign calling getWriter().recordRelocation
directly, bypassing generic code.
This patch:
* Introduces MCAsmBackend::relaxAlign to repla
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