https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/138495
>From 7938c63eb0883f47cffd02219400780ede01e559 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 08:47:42 +
Subject: [PATCH 1/3] [CodeGen][NPM] Port InitUndef to NPM
---
llvm/include/llvm/C
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/138491
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https://github.com/llvm/llvm-project/pull/138491
>From 3d1996a1d347eb14d6908d789307c0a3eef0568c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 5 May 2025 06:30:03 +
Subject: [PATCH] [AMDGPU][NPM] Complete optimized regalloc pipeline
Also fill in s
@@ -2174,7 +2174,44 @@ void AMDGPUCodeGenPassBuilder::addMachineSSAOptimization(
addPass(SIShrinkInstructionsPass());
}
+void AMDGPUCodeGenPassBuilder::addOptimizedRegAlloc(
+AddMachinePass &addPass) const {
+ if (EnableDCEInRA)
+insertPass(DeadMachineInstructionEli
@@ -285,7 +285,8 @@ template class
CodeGenPassBuilder {
FunctionPassManager FPM;
FPM.addPass(createFunctionToMachineFunctionPassAdaptor(std::move(MFPM)));
- FPM.addPass(InvalidateAnalysisPass());
+ // Since this is the last pass in the pipeline, we can
MacDue wrote:
I think it's reasonably safe given the general case (without hazard padding) is
well used and tested, and there's been no issues reported since this landed a
few weeks back.
https://github.com/llvm/llvm-project/pull/144693
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146083
>From 0017fe970358703c0227aa5dc31a952ddeddcc24 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 20:14:11 +0900
Subject: [PATCH 1/3] ARM: Unconditionally set eabi libcall calling convs in
Runt
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146083
>From 0017fe970358703c0227aa5dc31a952ddeddcc24 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 20:14:11 +0900
Subject: [PATCH 1/3] ARM: Unconditionally set eabi libcall calling convs in
Runt
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146084
>From 8dc9fc4ee600081d98afef0a5f3253f8c192348a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 23:23:01 +0900
Subject: [PATCH] ARM: Start moving runtime libcalls into tablegen
We still need
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146080
>From 74a0108ac5e37e351bb251137d11569433a001f0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 16:17:26 +0900
Subject: [PATCH] Lanai: Use TableGen to set libcall calling conventions
---
llv
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146081
>From e8b5aa10f291d51daabd1cbf35a4bbcca0d8320e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 16:35:14 +0900
Subject: [PATCH] MSP430: Move libcall CC setting to RuntimeLibcallsInfo
As a tem
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146081
>From e8b5aa10f291d51daabd1cbf35a4bbcca0d8320e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 16:35:14 +0900
Subject: [PATCH] MSP430: Move libcall CC setting to RuntimeLibcallsInfo
As a tem
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146082
>From 48fcd78593c4dcccbfd47b26cd15af8669bb630d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 19:10:30 +0900
Subject: [PATCH] RuntimeLibcalls: Remove table of soft float compare cond
codes
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146080
>From 74a0108ac5e37e351bb251137d11569433a001f0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 16:17:26 +0900
Subject: [PATCH] Lanai: Use TableGen to set libcall calling conventions
---
llv
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146082
>From 48fcd78593c4dcccbfd47b26cd15af8669bb630d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 19:10:30 +0900
Subject: [PATCH] RuntimeLibcalls: Remove table of soft float compare cond
codes
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/146084
>From 8dc9fc4ee600081d98afef0a5f3253f8c192348a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 23 Jun 2025 23:23:01 +0900
Subject: [PATCH] ARM: Start moving runtime libcalls into tablegen
We still need
https://github.com/arsenm closed
https://github.com/llvm/llvm-project/pull/147227
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@@ -0,0 +1,41 @@
+#ifdef LIBC_COPT_PRINTF_MODULAR
petrhosek wrote:
This file needs the copyright header.
https://github.com/llvm/llvm-project/pull/147426
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llvmbot wrote:
@llvm/pr-subscribers-coroutines
@llvm/pr-subscribers-llvm-transforms
Author: None (llvmbot)
Changes
Backport 038dc2c63b2db744be6afeea74b18be4938149e9
Requested by: @ChuanqiXu9
---
Full diff: https://github.com/llvm/llvm-project/pull/147448.diff
1 Files Affected:
- (modi
llvmbot wrote:
@ChuanqiXu9 What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/147448
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https://github.com/llvm/llvm-project/pull/147448
Backport 038dc2c63b2db744be6afeea74b18be4938149e9
Requested by: @ChuanqiXu9
>From 13f1e8e095bfbe59ce537a911e6fe95d940961ba Mon Sep 17 00:00:00 2001
From: Weibo He
Date: Tue, 3 Jun 2025 18:52:41 +0800
Subject:
leecheechen wrote:
Fixed a crash caused by incorrectly passing OptLevel to LoongArchDAGToDAGISel.
https://github.com/llvm/llvm-project/pull/144459
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arsenm wrote:
### Merge activity
* **Jul 8, 1:13 AM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/144979).
https://github.com/llvm/llvm-project/pull/144979
__
Author: shore
Date: 2025-07-08T08:55:33+08:00
New Revision: 6072d751726616fc4c88d856fadc857e4afab884
URL:
https://github.com/llvm/llvm-project/commit/6072d751726616fc4c88d856fadc857e4afab884
DIFF:
https://github.com/llvm/llvm-project/commit/6072d751726616fc4c88d856fadc857e4afab884.diff
LOG: fi
https://github.com/arsenm closed
https://github.com/llvm/llvm-project/pull/147226
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https://github.com/llvm/llvm-project/pull/147418
None
>From 03b555bc71ff35cee5b97a8c9d7883396d4d7f31 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Mon, 7 Jul 2025 12:44:41 -0700
Subject: [PATCH] Drive profile validator from opt
---
llvm/tools/opt/NewPM
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/147409
Backport a8a9a7f
Requested by: @sunfishcode
>From 9fd5816e48736cc51a118311e805d3e1f3758092 Mon Sep 17 00:00:00 2001
From: Alex Crichton
Date: Wed, 2 Jul 2025 05:26:30 +0200
Subject: [PATCH] [WebAssembly] Fix i
https://github.com/sunfishcode approved this pull request.
https://github.com/llvm/llvm-project/pull/147409
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llvmbot wrote:
@llvm/pr-subscribers-backend-webassembly
Author: None (llvmbot)
Changes
Backport a8a9a7f
Requested by: @sunfishcode
---
Full diff: https://github.com/llvm/llvm-project/pull/147409.diff
2 Files Affected:
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
https://github.com/llvmbot milestoned
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llvmbot wrote:
@sunfishcode What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/147409
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llvmbot wrote:
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-backend-powerpc
Author: Lei Huang (lei137)
Changes
Add clang builtins for DMF VSX Vector floats:
```
void __builtin_mma_dmxvf16gerx2 (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmxvf16gerx2nn (__dmr1024 *, __vector
https://github.com/lei137 created
https://github.com/llvm/llvm-project/pull/147383
Add clang builtins for DMF VSX Vector floats:
```
void __builtin_mma_dmxvf16gerx2 (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmxvf16gerx2nn (__dmr1024 *, __vector_pair, vec_t);
void __builtin_mma_dmx
inbelic wrote:
Contemplating if I should split this into two prs. Will see if there is a nice
way to de-couple the improve and fix error portions of this.
https://github.com/llvm/llvm-project/pull/147350
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https://github.com/llvm/llvm-project/pull/147350
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@@ -4294,24 +4396,32 @@ static int64_t
determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
report_fatal_error(
"Alignment of scalable vectors > 16 bytes is not yet supported");
+int64_t &Offset = OffsetForObject(FI, ZPROffset, PPROffset);
Offset = a
@@ -19,6 +19,11 @@
namespace llvm {
+struct SVEStackSizes {
sdesmalen-arm wrote:
Should this be named `SVEStackOffsets` (given that they're used as signed
offsets)?
https://github.com/llvm/llvm-project/pull/142391
__
@@ -4227,10 +4310,20 @@ static bool getSVECalleeSaveSlotRange(const
MachineFrameInfo &MFI,
// Fills in the first and last callee-saved frame indices into
// Min/MaxCSFrameIndex, respectively.
// Returns the size of the stack.
-static int64_t determineSVEStackObjectOffsets(Mach
@@ -1605,25 +1634,19 @@ static bool isTargetWindows(const MachineFunction &MF) {
return MF.getSubtarget().isTargetWindows();
}
-static unsigned getStackHazardSize(const MachineFunction &MF) {
- return MF.getSubtarget().getStreamingHazardSize();
-}
-
// Convenience function
@@ -451,10 +454,36 @@ static unsigned getFixedObjectSize(const MachineFunction
&MF,
}
}
-/// Returns the size of the entire SVE stackframe (calleesaves + spills).
+static unsigned getStackHazardSize(const MachineFunction &MF) {
sdesmalen-arm wrote:
nit: ma
@@ -299,14 +297,20 @@ class AArch64FunctionInfo final : public
MachineFunctionInfo {
TailCallReservedStack = bytes;
}
- bool hasCalculatedStackSizeSVE() const { return HasCalculatedStackSizeSVE; }
+ void setStackSizeZPR(uint64_t S) {
+HasCalculatedStackSizeSVE = t
@@ -299,14 +297,20 @@ class AArch64FunctionInfo final : public
MachineFunctionInfo {
TailCallReservedStack = bytes;
}
- bool hasCalculatedStackSizeSVE() const { return HasCalculatedStackSizeSVE; }
+ void setStackSizeZPR(uint64_t S) {
+HasCalculatedStackSizeSVE = t
@@ -784,8 +785,8 @@ AArch64RegisterInfo::useFPForScavengingIndex(const
MachineFunction &MF) const {
assert((!MF.getSubtarget().hasSVE() ||
AFI->hasCalculatedStackSizeSVE()) &&
"Expected SVE area to be calculated by this point");
- return TFI.hasFP(MF) &&
@@ -644,7 +644,8 @@ bool AArch64RegisterInfo::hasBasePointer(const
MachineFunction &MF) const {
if (ST.hasSVE() || ST.isStreaming()) {
// Frames that have variable sized objects and scalable SVE objects,
// should always use a basepointer.
- if (!AFI->hasC
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/147315
>From 0fbfd74d23b6cd26ef0480f7b9061b2f4a745338 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Mon, 7 Jul 2025 15:13:00 +
Subject: [PATCH 1/2] [LifetimeSafety] Add script performance benchmarking
---
cla
@@ -171,6 +186,12 @@ struct InfoTreeNode {
return It;
}
+ std::optional get(DeviceInfo Info) {
+if (DeviceInfoMap.count(Info))
+ return &(*Children)[DeviceInfoMap[Info]];
+return std::nullopt;
arsenm wrote:
This is still a double map looku
@@ -171,6 +186,12 @@ struct InfoTreeNode {
return It;
}
+ std::optional get(DeviceInfo Info) {
+if (DeviceInfoMap.count(Info))
+ return &(*Children)[DeviceInfoMap[Info]];
+return std::nullopt;
jhuber6 wrote:
```suggestion
return !Devic
@@ -133,17 +139,21 @@ struct InfoTreeNode {
// * The same key can appear multiple times
std::unique_ptr> Children;
+ std::map DeviceInfoMap;
jhuber6 wrote:
Do these need to be sorted? Otherwise a dense map is more efficient.
https://github.com/llvm/llvm
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff HEAD~1 HEAD --extensions hpp,cpp --
offload/liboffload/src/Helpers.hpp offload/liboff
llvmbot wrote:
@llvm/pr-subscribers-offload
Author: Ross Brunton (RossBrunton)
Changes
Instead using strings to look up device information (which is brittle
and slow), use the new tags that the plugins specify when building the
nodes.
---
Full diff: https://github.com/llvm/llvm-project/p
https://github.com/RossBrunton created
https://github.com/llvm/llvm-project/pull/147318
Instead using strings to look up device information (which is brittle
and slow), use the new tags that the plugins specify when building the
nodes.
>From 4cce1eec173637a0e50655e10ad520a9821b9960 Mon Sep 17
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Ross Brunton (RossBrunton)
Changes
When generating the device info tree, nodes can be marked with an
offload Device Info value. The nodes can also look up children based
on this value.
---
Full diff: https://github.com/llvm/llvm-
https://github.com/RossBrunton created
https://github.com/llvm/llvm-project/pull/147317
When generating the device info tree, nodes can be marked with an
offload Device Info value. The nodes can also look up children based
on this value.
>From 9b79557e7a536ccd4b02365c9dd98a4ef69f87e1 Mon Sep 1
github-actions[bot] wrote:
:warning: Python code formatter, darker found issues in your code. :warning:
You can test this locally with the following command:
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View the di
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llvmbot wrote:
@llvm/pr-subscribers-clang-analysis
Author: Utkarsh Saxena (usx95)
Changes
This patch introduces the core dataflow analysis infrastructure for the C++
Lifetime Safety checker. This change implements the logic to propagate "loan"
information across the control-flow graph. T
https://github.com/usx95 ready_for_review
https://github.com/llvm/llvm-project/pull/147295
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>From e870b040c4ef29b7ca2e50c1fc0ab5a2446f5cf6 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sun, 6 Jul 2025 19:12:55 +
Subject: [PATCH] [LifetimeSafety] Propagate loans using dataflow analysis
---
cla
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https://github.com/llvm/llvm-project/pull/147295
>From dd2dd838f44ebeb6d45f75af2934159ee61b385b Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sun, 6 Jul 2025 19:12:55 +
Subject: [PATCH] [LifetimeSafety] Propagate loans using dataflow analysis
---
cla
https://github.com/DanielKristofKiss approved this pull request.
https://github.com/llvm/llvm-project/pull/147225
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https://github.com/DanielKristofKiss approved this pull request.
lgtm
https://github.com/llvm/llvm-project/pull/147226
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https://github.com/jhuber6 approved this pull request.
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llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Sam Tebbs (SamTebbs33)
Changes
This PR bundles partial reductions inside the VPExpressionRecipe class.
Depends on https://github.com/llvm/llvm-project/pull/147255 .
---
Patch is 202.63 KiB, truncated to 20.00 KiB below, full ve
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Emit a context error and delete the instruction. This
allows removing the AMDGPU hack where some atomic libcalls
are falsely added. NVPTX also later copied the same hack,
so remove it there too.
For
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/147300?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/147300
Emit a context error and delete the instruction. This
allows removing the AMDGPU hack where some atomic libcalls
are falsely added. NVPTX also later copied the same hack,
so remove it there too.
For now just emit
https://github.com/usx95 updated
https://github.com/llvm/llvm-project/pull/147295
>From 2e4261b02b6230a8c79f01a673cc3030cfff3ea7 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sun, 6 Jul 2025 19:12:55 +
Subject: [PATCH 1/6] [LifetimeSafety] Propagate loans using dataflow analysis
---
https://github.com/usx95 created
https://github.com/llvm/llvm-project/pull/147295
None
>From 2e4261b02b6230a8c79f01a673cc3030cfff3ea7 Mon Sep 17 00:00:00 2001
From: Utkarsh Saxena
Date: Sun, 6 Jul 2025 19:12:55 +
Subject: [PATCH 1/6] [LifetimeSafety] Propagate loans using dataflow analysis
llvmbot wrote:
@llvm/pr-subscribers-mlir-llvm
@llvm/pr-subscribers-mlir
Author: Michael Kruse (Meinersbur)
Changes
Support for translating the operations introduced in #144785 to LLVM-IR.
In order to keep the lowering simple, `OpenMPIRBuider::unrollLoopHeuristic` is
applied when encounte
https://github.com/Meinersbur ready_for_review
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https://github.com/DanielKristofKiss approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/147226
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https://github.com/Meinersbur updated
https://github.com/llvm/llvm-project/pull/147069
>From da2613d525deb4edcf0fac41e865ca0510c75210 Mon Sep 17 00:00:00 2001
From: Michael Kruse
Date: Fri, 4 Jul 2025 16:26:20 +0200
Subject: [PATCH] omp.canonical_loop and omp.unroll_heuristic lowering
---
...
https://github.com/ssahasra edited
https://github.com/llvm/llvm-project/pull/147257
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@@ -669,6 +679,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-WGP-NEXT:s_wait_kmcnt 0x0
; GFX12-WGP-NEXT:s_wait_storecnt 0x0
; GFX12-WGP-NEXT:global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
+; GFX12-WGP-NEXT:s_wait_loadcnt 0x3f
Author: Corentin Jabot
Date: 2025-07-07T14:05:22+02:00
New Revision: 902eaa1d5e24beb2a7129c61dfa84759a668f62f
URL:
https://github.com/llvm/llvm-project/commit/902eaa1d5e24beb2a7129c61dfa84759a668f62f
DIFF:
https://github.com/llvm/llvm-project/commit/902eaa1d5e24beb2a7129c61dfa84759a668f62f.diff
@@ -669,6 +679,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-WGP-NEXT:s_wait_kmcnt 0x0
; GFX12-WGP-NEXT:s_wait_storecnt 0x0
; GFX12-WGP-NEXT:global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
+; GFX12-WGP-NEXT:s_wait_loadcnt 0x3f
@@ -1401,8 +1401,8 @@ static void analyzeCostOfVecReduction(const IntrinsicInst
&II,
TTI::CastContextHint::None, CostKind, RedOp);
CostBeforeReduction = ExtCost * 2 + MulCost + Ext2Cost;
-CostAfterReduction =
-TTI.getMulAccReductio
@@ -2757,6 +2757,12 @@ class VPExpressionRecipe : public VPSingleDefRecipe {
/// vector operands, performing a reduction.add on the result, and adding
/// the scalar result to a chain.
MulAccReduction,
+/// Represent an inloop multiply-accumulate reduction, mult
@@ -5538,7 +5538,7 @@
LoopVectorizationCostModel::getReductionPatternCost(Instruction *I,
TTI::CastContextHint::None, CostKind, RedOp);
InstructionCost RedCost = TTI.getMulAccReductionCost(
-IsUnsigned, RdxDesc.getRecurrenceType(), Ext
@@ -3116,7 +3116,10 @@ class BasicTTIImplBase : public
TargetTransformInfoImplCRTPBase {
InstructionCost
getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty,
+ bool Negated,
TTI::TargetCostKind CostKind) co
@@ -2725,6 +2729,31 @@ void VPExpressionRecipe::print(raw_ostream &O, const
Twine &Indent,
O << ")";
break;
}
+ case ExpressionTypes::ExtNegatedMulAccReduction: {
david-arm wrote:
Is there a way to commonise this with the ExtMulAccReduction case if
@@ -1645,8 +1645,10 @@ class TargetTransformInfo {
/// extensions. This is the cost of as:
/// ResTy vecreduce.add(mul (A, B)).
/// ResTy vecreduce.add(mul(ext(Ty A), ext(Ty B)).
+ /// The multiply can optionally be negated, which signifies that it is a sub
+ /// reduct
@@ -669,6 +679,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-WGP-NEXT:s_wait_kmcnt 0x0
; GFX12-WGP-NEXT:s_wait_storecnt 0x0
; GFX12-WGP-NEXT:global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
+; GFX12-WGP-NEXT:s_wait_loadcnt 0x3f
@@ -669,6 +679,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-WGP-NEXT:s_wait_kmcnt 0x0
; GFX12-WGP-NEXT:s_wait_storecnt 0x0
; GFX12-WGP-NEXT:global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
+; GFX12-WGP-NEXT:s_wait_loadcnt 0x3f
@@ -669,6 +679,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-WGP-NEXT:s_wait_kmcnt 0x0
; GFX12-WGP-NEXT:s_wait_storecnt 0x0
; GFX12-WGP-NEXT:global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
+; GFX12-WGP-NEXT:s_wait_loadcnt 0x3f
@@ -669,6 +679,7 @@ define amdgpu_kernel void @global_volatile_store_1(
; GFX12-WGP-NEXT:s_wait_kmcnt 0x0
; GFX12-WGP-NEXT:s_wait_storecnt 0x0
; GFX12-WGP-NEXT:global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS
+; GFX12-WGP-NEXT:s_wait_loadcnt 0x3f
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From b386d126b9f560bf203fd044d81575ddfad2a8c6 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From b386d126b9f560bf203fd044d81575ddfad2a8c6 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
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