[llvm-branch-commits] [flang] [flang][OpenMP] Basic mapping of `do concurrent ... reduce` to OpenMP (PR #146033)

ergawy wrote: > LGTM but please could you add a test that covers every region. Thanks for the review. Done. https://github.com/llvm/llvm-project/pull/146033 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org

[llvm-branch-commits] [flang] [flang][OpenMP] Basic mapping of `do concurrent ... reduce` to OpenMP (PR #146033)

https://github.com/ergawy updated https://github.com/llvm/llvm-project/pull/146033 >From f7837d52f95340e627852ebaa34407ac318156c5 Mon Sep 17 00:00:00 2001 From: ergawy Date: Fri, 27 Jun 2025 00:58:08 -0500 Subject: [PATCH 1/2] [flang][OpenMP] Basic mapping of `do concurrent ... reduce` to Open

[llvm-branch-commits] [flang] [NFC][flang] Move `ReductionProcessor` to `Lower/Support`. (PR #146025)

https://github.com/ergawy updated https://github.com/llvm/llvm-project/pull/146025 >From 6a7c71ecaebccf4d8dddc7373384b4df918973c2 Mon Sep 17 00:00:00 2001 From: ergawy Date: Thu, 26 Jun 2025 23:30:04 -0500 Subject: [PATCH 1/2] [NFC][flang] Move `ReductionProcessor` to `Lower/Support`. With #1

[llvm-branch-commits] [flang] [flang][fir] Small clean-up in `fir_DoConcurrentLoopOp`'s defintion (PR #146028)

https://github.com/ergawy updated https://github.com/llvm/llvm-project/pull/146028 >From 3e2bdf5a8d346f6817f86e98f098e3f6cc47e0b0 Mon Sep 17 00:00:00 2001 From: ergawy Date: Fri, 27 Jun 2025 00:05:42 -0500 Subject: [PATCH] [flang][fir] Small clean-up in `fir_DoConcurrentLoopOp`'s defintion Re

[llvm-branch-commits] [flang] [flang][fir] Small clean-up in `fir_DoConcurrentLoopOp`'s defintion (PR #146028)

https://github.com/ergawy updated https://github.com/llvm/llvm-project/pull/146028 >From 105ac7ade82ccfdfd0b33d30dc46c84a94df884b Mon Sep 17 00:00:00 2001 From: ergawy Date: Fri, 27 Jun 2025 00:05:42 -0500 Subject: [PATCH] [flang][fir] Small clean-up in `fir_DoConcurrentLoopOp`'s defintion Re

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/146305 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/146305 >From 165b8e3d9d18350e2d976aac8614f093f6189a6a Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Sun, 29 Jun 2025 23:47:02 -0400 Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 Co-authored-

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/146305 >From 165b8e3d9d18350e2d976aac8614f093f6189a6a Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Sun, 29 Jun 2025 23:47:02 -0400 Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 Co-authored-

[llvm-branch-commits] [flang] [flang][OpenMP] Basic mapping of `do concurrent ... reduce` to OpenMP (PR #146033)

https://github.com/ergawy updated https://github.com/llvm/llvm-project/pull/146033 >From 34a5df1725f185ba91d9a41ab6286635537502dc Mon Sep 17 00:00:00 2001 From: ergawy Date: Fri, 27 Jun 2025 00:58:08 -0500 Subject: [PATCH] [flang][OpenMP] Basic mapping of `do concurrent ... reduce` to OpenMP

[llvm-branch-commits] [flang] [NFC][flang] Move `ReductionProcessor` to `Lower/Support`. (PR #146025)

https://github.com/ergawy updated https://github.com/llvm/llvm-project/pull/146025 >From 6a7c71ecaebccf4d8dddc7373384b4df918973c2 Mon Sep 17 00:00:00 2001 From: ergawy Date: Thu, 26 Jun 2025 23:30:04 -0500 Subject: [PATCH] [NFC][flang] Move `ReductionProcessor` to `Lower/Support`. With #145837

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/146305 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/146305 >From f236297e3e4f40929dd214f6a3a92f28fc160cd1 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Sun, 29 Jun 2025 23:47:02 -0400 Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 Co-authored-

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/146305 >From f236297e3e4f40929dd214f6a3a92f28fc160cd1 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Sun, 29 Jun 2025 23:47:02 -0400 Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 Co-authored-

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

llvmbot wrote: @llvm/pr-subscribers-clang @llvm/pr-subscribers-backend-amdgpu Author: Shilei Tian (shiltian) Changes Co-authored-by: Shilei Tian --- Patch is 48.58 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/146305.diff

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

shiltian wrote: > > Co-authored-by: Shilei Tian [i...@tianshilei.me](mailto:i...@tianshilei.me) > > Co authored by yourself? Same as its parent. https://github.com/llvm/llvm-project/pull/146305 ___ llvm-branch-commits mailing list llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

arsenm wrote: > Co-authored-by: Shilei Tian [i...@tianshilei.me](mailto:i...@tianshilei.me) Co authored by yourself? https://github.com/llvm/llvm-project/pull/146305 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://list

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

shiltian wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/146305?utm_source=stack-comment-downstack-mergeability-warning"

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250 (PR #146305)

https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/146305 Co-authored-by: Shilei Tian >From cb1103c52ec9c8bf1dac1f27136e4d524ce3cc4c Mon Sep 17 00:00:00 2001 From: "Mekhanoshin, Stanislav" Date: Sun, 29 Jun 2025 23:19:25 -0400 Subject: [PATCH] [AMDGPU] Add support f

[llvm-branch-commits] [llvm] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR (PR #146075)

@@ -416,6 +416,60 @@ entry: ret void } +; Check that ptradds can be lowered to disjoint ORs. +define ptr @gep_disjoint_or(ptr %base) { +; GFX942-LABEL: gep_disjoint_or: +; GFX942: ; %bb.0: +; GFX942-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT:v_

[llvm-branch-commits] [llvm] [AMDGPU][SDAG] DAGCombine PTRADD -> disjoint OR (PR #146075)

@@ -15136,6 +15136,41 @@ SDValue SITargetLowering::performPtrAddCombine(SDNode *N, return Folded; } + // Transform (ptradd a, b) -> (or disjoint a, b) if it is equivalent and if + // that transformation can't block an offset folding at any use of the ptradd. + //

[llvm-branch-commits] [llvm] [SelectionDAG] Deal with POISON for INSERT_VECTOR_ELT/INSERT_SUBVECTOR (part 2) (PR #143103)

@@ -5454,6 +5454,59 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, } return true; + case ISD::INSERT_SUBVECTOR: { +if (Op.getValueType().isScalableVector()) + break; +SDValue Src = Op.getOperand(0); +SDValue Sub = Op.getOperand(1)

[llvm-branch-commits] [llvm] [SelectionDAG] Deal with POISON for INSERT_VECTOR_ELT/INSERT_SUBVECTOR (part 2) (PR #143103)

@@ -5454,6 +5454,59 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, } return true; + case ISD::INSERT_SUBVECTOR: { +if (Op.getValueType().isScalableVector()) + break; +SDValue Src = Op.getOperand(0); +SDValue Sub = Op.getOperand(1)