https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/145639
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llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Matt Arsenault (arsenm)
Changes
Write this in a more predicate-apply style instead of the
switch.
---
Full diff: https://github.com/llvm/llvm-project/pull/145639.diff
1 Files Affected:
- (modified) llvm/lib/IR/RuntimeLibcalls.
https://github.com/jh7370 approved this pull request.
LGTM, thanks. Probably want to wait for @MaskRay for final sign-off, but if
he's too busy, land it in a couple of days anyway.
https://github.com/llvm/llvm-project/pull/145009
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https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/145638
Add a predicate function following the example of __sincos_stret
>From 5266f79e89936261972af847253d2b017145e141 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 25 Jun 2025 14:23:21 +0900
Subject: [PATCH
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
Author: Matt Arsenault (arsenm)
Changes
Write this in a more predicate-apply style instead of the
switch.
---
Full diff: https://github.com/llvm/llvm-project/pull/145639.diff
1 Files Affected:
- (modified) llvm/lib/IR/RuntimeLibcalls.cpp (+2-
https://github.com/arsenm ready_for_review
https://github.com/llvm/llvm-project/pull/145638
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llvmbot wrote:
@llvm/pr-subscribers-mc
@llvm/pr-subscribers-backend-aarch64
Author: Matt Arsenault (arsenm)
Changes
Add a predicate function following the example of __sincos_stret
---
Full diff: https://github.com/llvm/llvm-project/pull/145638.diff
2 Files Affected:
- (modified) llvm/
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145639?utm_source=stack-comment-downstack-mergeability-warning";
arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145638?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/145639
Write this in a more predicate-apply style instead of the
switch.
>From 2fdd40315244cf87324ec124e232549b5c611e92 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 25 Jun 2025 14:42:24 +0900
Subject: [PATC
https://github.com/aemerson updated
https://github.com/llvm/llvm-project/pull/145613
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https://github.com/aemerson edited
https://github.com/llvm/llvm-project/pull/145613
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@@ -129,6 +147,245 @@ bool AlwaysInlineImpl(
return Changed;
}
+/// Promote allocas to registers if possible.
+static void promoteAllocas(
+Function *Caller, SmallPtrSetImpl &AllocasToPromote,
+function_ref &GetAssumptionCache) {
+ if (AllocasToPromote.empty())
+
https://github.com/MaskRay approved this pull request.
https://github.com/llvm/llvm-project/pull/145009
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Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145484?utm_source=stack-comment-downstack-mergeability-warning
Author: Thurston Dang
Date: 2025-06-24T15:52:53-07:00
New Revision: ded97817c5f465aaea9f923d6ec247c8ace0f0c2
URL:
https://github.com/llvm/llvm-project/commit/ded97817c5f465aaea9f923d6ec247c8ace0f0c2
DIFF:
https://github.com/llvm/llvm-project/commit/ded97817c5f465aaea9f923d6ec247c8ace0f0c2.diff
https://github.com/aengelke updated
https://github.com/llvm/llvm-project/pull/145009
>From db5463b1af5c1c425866979dcf85ee5919c8a75d Mon Sep 17 00:00:00 2001
From: Alexis Engelke
Date: Mon, 23 Jun 2025 08:50:34 +
Subject: [PATCH 1/5] address comments + add reloctable test
Created using spr
@@ -0,0 +1,113 @@
+//===- MCGOFFAttributes.h - Attributes of GOFF symbols
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -2160,7 +2160,22 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr
addrspace(1) %out, <2 x flo
; IEEE-GOODFREXP-NEXT:[[TMP38:%.*]] = insertelement <2 x float> poison,
float [[TMP27]], i64 0
; IEEE-GOODFREXP-NEXT:[[MD_1ULP_UNDEF:%.*]] = insertelement <2 x float
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/145578
>From 6c6ac88c73fbffa56983bf8a0cf269e0bc59cb14 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Tue, 24 Jun 2025 09:50:40 -0700
Subject: [PATCH] [pgo] add means to specify "unknown" MD_prof
---
llvm/include/
https://github.com/rymrg edited https://github.com/llvm/llvm-project/pull/145540
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@@ -0,0 +1,30 @@
+; Test branch weight unknown validation
+
+; RUN: split-file %s %t
+; RUN: opt -passes=verify %t/correct.ll --disable-output
+; RUN: not opt -passes=verify %t/incorrect.ll --disable-output
mtrofin wrote:
yes, and I'll move these to llvm/test/Ver
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/145578
>From e2f673682594ceafc73e5b7765934caabffd4907 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Tue, 24 Jun 2025 09:50:40 -0700
Subject: [PATCH] [pgo] add means to specify "unknown" MD_prof
---
llvm/include/
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/145584
>From a9742de1b38e1745268e970845d187108ba292bf Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Tue, 24 Jun 2025 13:14:09 -0700
Subject: [PATCH] [IR][PGO] Verify the structure of `VP` metadata.
---
llvm/lib/
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/145578
>From 6c6ac88c73fbffa56983bf8a0cf269e0bc59cb14 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Tue, 24 Jun 2025 09:50:40 -0700
Subject: [PATCH] [pgo] add means to specify "unknown" MD_prof
---
llvm/include/
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/145584
>From a9742de1b38e1745268e970845d187108ba292bf Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Tue, 24 Jun 2025 13:14:09 -0700
Subject: [PATCH] [IR][PGO] Verify the structure of `VP` metadata.
---
llvm/lib/
mtrofin wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/145578?utm_source=stack-comment-downstack-mergeability-warning";
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp,h --
llvm/include/llvm/IR/ProfDataUtils.h llvm/lib/IR/Pr
https://github.com/mtrofin created
https://github.com/llvm/llvm-project/pull/145578
None
>From 1a15250e8b8cbdbb17613641fbd6003b4a901606 Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Tue, 24 Jun 2025 09:50:40 -0700
Subject: [PATCH] [pgo] add means to specify "unknown" MD_prof
---
llvm/in
Author: Michael Buch
Date: 2025-06-24T11:32:34+01:00
New Revision: a935d5ab75b11f8fc1f1196e3ee4bcd15a9102ce
URL:
https://github.com/llvm/llvm-project/commit/a935d5ab75b11f8fc1f1196e3ee4bcd15a9102ce
DIFF:
https://github.com/llvm/llvm-project/commit/a935d5ab75b11f8fc1f1196e3ee4bcd15a9102ce.diff
@@ -0,0 +1,67 @@
+# RUN: yaml2obj %s -o %t
+# RUN: llvm-objdump %t -d --symbolize-operands --no-show-raw-insn
--no-leading-addr | \
+# RUN: FileCheck %s --match-full-lines -DABS_ADRP_VAL=0x6000
+# RUN: llvm-objdump %t -d --symbolize-operands --no-show-raw-insn
--no-leading-add
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: None (rymrg)
Changes
Initial RSan without value extension
https://discourse.llvm.org/t/rfc-robustess-sanitizer/86831/
Paper: https://doi.org/10.1145/3729277
Preprint version: https://arxiv.org/pdf/2504.15036
Proper race d
https://github.com/rymrg updated
https://github.com/llvm/llvm-project/pull/145540
>From 89b3a5541fadc69b721d584a95d695e809eb1f78 Mon Sep 17 00:00:00 2001
From: rymrg <54061433+ry...@users.noreply.github.com>
Date: Mon, 23 Jun 2025 21:55:32 +0300
Subject: [PATCH 1/2] RSan: https://doi.org/10.1145
@@ -0,0 +1,67 @@
+# RUN: yaml2obj %s -o %t
+# RUN: llvm-objdump %t -d --symbolize-operands --no-show-raw-insn
--no-leading-addr | \
+# RUN: FileCheck %s --match-full-lines -DABS_ADRP_VAL=0x6000
+# RUN: llvm-objdump %t -d --symbolize-operands --no-show-raw-insn
--no-leading-add
https://github.com/rymrg edited https://github.com/llvm/llvm-project/pull/145540
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Author: Qinkun Bao
Date: 2025-06-24T11:37:27-04:00
New Revision: c0aa1f007ad7d13e7e8c7949f4d7271f870c7f58
URL:
https://github.com/llvm/llvm-project/commit/c0aa1f007ad7d13e7e8c7949f4d7271f870c7f58
DIFF:
https://github.com/llvm/llvm-project/commit/c0aa1f007ad7d13e7e8c7949f4d7271f870c7f58.diff
LO
https://github.com/uweigand edited
https://github.com/llvm/llvm-project/pull/133799
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@@ -1751,6 +1750,25 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
Inst.addOperand(MCOperand::createImm(0));
}
+ bool isTrap(const MCInst &Inst) const override {
+if (Inst.getOpcode() != AArch64::BRK)
+ return false;
+// Only match the immediate val
https://github.com/kbeyls commented:
Thanks, mostly looks good, I only have 1 nitpicky comment about the underlying
reason why the pauth analyzer should have a slightly different "definition" of
what is considered a tail call versus BOLT overall.
https://github.com/llvm/llvm-project/pull/13722
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/141591
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https://github.com/bjope updated
https://github.com/llvm/llvm-project/pull/143105
From c007c75562eea85cfcac523c27599d5293c484fe Mon Sep 17 00:00:00 2001
From: Bjorn Pettersson
Date: Sat, 31 May 2025 09:37:27 +0200
Subject: [PATCH] [SelectionDAG] Deal with POISON for
INSERT_VECTOR_ELT/INSERT_SU
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145329
>From 7c9ac3cdc769e989d87296bfa8998434d6611045 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 03:51:19 -0400
Subject: [PATCH] [AMDGPU][SDAG] Test ISD::PTRADD handling in various special
https://github.com/uweigand commented:
There doesn't appear to be any asm output for these?
https://github.com/llvm/llvm-project/pull/144437
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jayfoad wrote:
I don't understand the high level motivation here. "Normal"
combining/simplification order is to visit the operands of an instruction
before you visit the instruction itself. That way the "visit" function can
assume that the operands have already been simplified. GlobalISel comb
@@ -109,6 +110,7 @@ class AMDGPUCodeGenPrepareImpl
bool FlowChanged = false;
mutable Function *SqrtF32 = nullptr;
mutable Function *LdexpF32 = nullptr;
+ mutable SetVector DeadVals;
arsenm wrote:
I don't think this needs to be a set, the iteration shoul
@@ -285,28 +287,19 @@ bool AMDGPUCodeGenPrepareImpl::run() {
BreakPhiNodesCache.clear();
bool MadeChange = false;
- Function::iterator NextBB;
- for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; FI = NextBB)
{
-BasicBlock *BB = &*FI;
-NextBB = std:
@@ -1634,29 +1634,18 @@ define float @v_recip_sqrt_f32_ulp25_contract(float %x)
{
; IR-IEEE-SDAG-LABEL: v_recip_sqrt_f32_ulp25_contract:
; IR-IEEE-SDAG: ; %bb.0:
; IR-IEEE-SDAG-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; IR-IEEE-SDAG-NEXT:s_mov_b32 s4, 0xf800
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/145484
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@@ -0,0 +1,106 @@
+//===- MCGOFFAttributes.h - Attributes of GOFF symbols
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/uweigand commented:
Looks generally good to me now, still a few comments inline.
https://github.com/llvm/llvm-project/pull/133799
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aengelke wrote:
Done. The command line help doesn't give any indication on supported
architectures.
https://github.com/llvm/llvm-project/pull/145009
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https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/145330
>From 286252e31314dd852ef854918068f1ca0023023c Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Tue, 17 Jun 2025 04:03:53 -0400
Subject: [PATCH] [AMDGPU][SDAG] Handle ISD::PTRADD in various special cases
T
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/142778
>From d6f5395374f9bef864b0442f8fc62ba260910bdd Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 4 Jun 2025 09:48:02 -0400
Subject: [PATCH] [AMDGPU][SDAG] Handle ISD::PTRADD in
SelectionDAGAddressAnaly
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/143672
>From 74777534d4ee80311ee342af11b4d5a87564f137 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 11 Jun 2025 05:14:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Tests for target-specific ISD::PTRADD combines
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/142777
>From ade6820ff56d755a7155cd170d7b1ebf24bc8aef Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
Selection
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/143673
>From 91bd709f8f7b0f8a05578bd1291295b5a8d1b6c1 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Wed, 11 Jun 2025 05:48:45 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add target-specific ISD::PTRADD combines
This
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 10a9e08e314dcb5a57fd1c6a6e818a4146ed9210 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 76be3031e6f1195263d63fd09d2f0087a7f5e853 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141591
>From 10a9e08e314dcb5a57fd1c6a6e818a4146ed9210 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 12:29:02 +0200
Subject: [PATCH 1/2] [AMDGPU] Add KnownBits simplification combines to
RegBankCombi
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/141589
>From 76be3031e6f1195263d63fd09d2f0087a7f5e853 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Tue, 27 May 2025 11:16:16 +0200
Subject: [PATCH 1/2] [AMDGPU] Move S_BFE lowering into RegBankCombiner
---
llvm/li
@@ -0,0 +1,77 @@
+# RUN: llvm-mc --triple=aarch64-elf --filetype=obj < %s | llvm-objdump -d -r
--symbolize-operands --no-show-raw-insn --no-leading-addr - | FileCheck %s
--match-full-lines
jh7370 wrote:
Nit: let's split this line over multiple lines for readabi
@@ -0,0 +1,77 @@
+# RUN: llvm-mc --triple=aarch64-elf --filetype=obj < %s | llvm-objdump -d -r
--symbolize-operands --no-show-raw-insn --no-leading-addr - | FileCheck %s
--match-full-lines
+
+# CHECK: :
+# CHECK-NEXT: b
+# CHECK-NEXT: tbz x0, #0x2c,
+# CHECK-NEXT: :
+
@@ -1784,6 +1784,10 @@ void AArch64InstPrinter::printAlignedLabel(const MCInst
*MI, uint64_t Address,
unsigned OpNum,
const MCSubtargetInfo &STI,
ra
@@ -0,0 +1,77 @@
+# RUN: llvm-mc --triple=aarch64-elf --filetype=obj < %s | llvm-objdump -d -r
--symbolize-operands --no-show-raw-insn --no-leading-addr - | FileCheck %s
--match-full-lines
+
+# CHECK: :
+# CHECK-NEXT: b
+# CHECK-NEXT: tbz x0, #0x2c,
+# CHECK-NEXT: :
+
https://github.com/jh7370 edited
https://github.com/llvm/llvm-project/pull/145009
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@@ -1813,6 +1817,12 @@ void AArch64InstPrinter::printAdrAdrpLabel(const MCInst
*MI, uint64_t Address,
unsigned OpNum,
const MCSubtargetInfo &STI,
ra
@@ -0,0 +1,77 @@
+# RUN: llvm-mc --triple=aarch64-elf --filetype=obj < %s | llvm-objdump -d -r
--symbolize-operands --no-show-raw-insn --no-leading-addr - | FileCheck %s
--match-full-lines
+
+# CHECK: :
+# CHECK-NEXT: b
+# CHECK-NEXT: tbz x0, #0x2c,
+# CHECK-NEXT: :
+
https://github.com/jh7370 commented:
Basically looks good. Just some typos and other nits. Also, the documentation
for the option says it works only for PPC and X86. Please could you update this
and double-check whether the command-line help has the same note.
https://github.com/llvm/llvm-proj
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