arsenm wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/142536?utm_source=stack-comment-downstack-mergeability-warning";
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/142538
Directly write to the output instead of building a string to
print.
>From d0644fa28031eaa54bff4819fb165830ea87c719 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 2 Jun 2025 16:03:38 +0200
Subject: [PAT
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/142537
Previously this always printed the standard name if the function
was available, leaving any custom name override untested. Print the
target's name instead. The message should possibly include the standard
name for
https://github.com/vitalybuka updated
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llvmbot wrote:
@llvm/pr-subscribers-bolt
Author: Amir Ayupov (aaupov)
Changes
Record the number of function invocations from external code - code
outside the binary, which may include JIT code and DSOs.
The purpose of it is to exclude external entry counts from call graph
flow conservatio
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llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: Vitaly Buka (vitalybuka)
Changes
`IncomingVals`, `IncomingLocs`, `Worklist` into class members.
They are all DFS state related, as `Visited`. But visited is already a
class member.
On it's own the patch has no value, but it
simpl
https://github.com/joaosaffran created
https://github.com/llvm/llvm-project/pull/142492
- adds parsing from metadata into dxcontainer binary
- adds validations as described in the spec
- adds testing scenarios
Closes: #[126640](https://github.com/llvm/llvm-project/issues/126640)
>From 3e6b07e11
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@llvm/pr-subscribers-llvm-binary-utilities
Author: None (joaosaffran)
Changes
- adds parsing from metadata into dxcontainer binary
- adds validations as described in the spec
- adds testing scenarios
Closes: #[126640](https://github.com/l
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vitalybuka wrote:
> LGTM with context of the follow up. By itself, this patch is probably making
> things worse
Yes, Incoming* here are better as parameters.
I will wait with landing for #142474 accepted
https://github.com/llvm/llvm-project/pull/142468
https://github.com/fmayer approved this pull request.
LGTM with context of the follow up. By itself, this patch is probably making
things worse
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@@ -281,18 +281,44 @@ struct AllocaInfo {
}
};
+template class VectorWithUndo {
+ SmallVector Vals;
+ SmallVector, 8> Undo;
+
+public:
+ void undo(size_t S) {
+while (S < Undo.size()) {
+ Vals[Undo.back().first] = Undo.back().second;
+ Undo.pop_back();
+
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llvmbot wrote:
@llvm/pr-subscribers-clang-format
Author: None (llvmbot)
Changes
Backport 7bf5862dbfda590282f50b14e6d7d5f990bf1900
Requested by: @owenca
---
Full diff: https://github.com/llvm/llvm-project/pull/142482.diff
2 Files Affected:
- (modified) clang/lib/Format/TokenAnnotator.c
llvmbot wrote:
@HazardyKnusperkeks What do you think about merging this PR to the release
branch?
https://github.com/llvm/llvm-project/pull/142482
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/142482
Backport 7bf5862dbfda590282f50b14e6d7d5f990bf1900
Requested by: @owenca
>From 6481daabf7354eb69807f3d7ba1bdd1e26406c32 Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Mon, 2 Jun 2025 13:35:27 -0700
Subject: [PAT
https://github.com/vitalybuka updated
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efriedma-quic wrote:
In the implementation you're interested in, is there not a hazard between PPRs
and GPRs?
What's the interaction between this and aarch64-enable-zpr-predicate-spills?
https://github.com/llvm/llvm-project/pull/142392
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llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: Vitaly Buka (vitalybuka)
Changes
When BasicBlock has a large number of allocas, and
successors, we had to copy entire IncomingVals and
IncomingLocs vectors for successors.
Additional changes in IncomingVals and
IncomingLocs are i
https://github.com/vitalybuka created
https://github.com/llvm/llvm-project/pull/142474
When BasicBlock has a large number of allocas, and
successors, we had to copy entire IncomingVals and
IncomingLocs vectors for successors.
Additional changes in IncomingVals and
IncomingLocs are infrequent (o
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Qinkun Bao (qinkunbao)
Changes
See https://github.com/llvm/llvm-project/issues/139128
If multiple entries match the source, than the latest entry takes the
precedence.
---
Full diff: https://github.com/llvm/llvm-project/pull/142472.diff
https://github.com/qinkunbao edited
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https://github.com/qinkunbao created
https://github.com/llvm/llvm-project/pull/142472
See https://github.com/llvm/llvm-project/issues/139128
If multiple entries match the source, than the latest entry takes the
precedence.
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https://github.com/vitalybuka created
https://github.com/llvm/llvm-project/pull/142468
`IncomingVals`, `IncomingLocs`, `Worklist` into class members.
They are all DFS state related, as `Visited`. But visited is already a
class member.
On it's own the patch has no value, but it
simplify stuff in
https://github.com/qinkunbao updated
https://github.com/llvm/llvm-project/pull/142456
>From c0d1cb94966a24e12525bb5c1d863e43cd13e3c2 Mon Sep 17 00:00:00 2001
From: Qinkun Bao
Date: Mon, 2 Jun 2025 19:10:16 +
Subject: [PATCH 1/2] Change the test.
Created using spr 1.3.6
---
...relist.test
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: Vitaly Buka (vitalybuka)
Changes
Additionally handler successors in regular order, so that two successors
cases are handled exactly as before, so we need to less tests.
Additionally reverse order here results in more
natural 'phi
https://github.com/vitalybuka created
https://github.com/llvm/llvm-project/pull/142464
Additionally handler successors in regular order, so that two successors
cases are handled exactly as before, so we need to less tests.
Additionally reverse order here results in more
natural 'phi' arguments
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Qinkun Bao (qinkunbao)
Changes
See https://github.com/llvm/llvm-project/issues/139128
If multiple entries match the source, than the latest entry takes the
precedence.`
---
Full diff: https://github.com/llvm/llvm-project/pull/142456.diff
https://github.com/qinkunbao updated
https://github.com/llvm/llvm-project/pull/142456
>From c0d1cb94966a24e12525bb5c1d863e43cd13e3c2 Mon Sep 17 00:00:00 2001
From: Qinkun Bao
Date: Mon, 2 Jun 2025 19:10:16 +
Subject: [PATCH] Change the test.
Created using spr 1.3.6
---
...relist.test => a
Author: Chao Chen
Date: 2025-06-02T14:14:03-05:00
New Revision: 0c04af9c9748947bf65b411b8c41c90cf6ba16ed
URL:
https://github.com/llvm/llvm-project/commit/0c04af9c9748947bf65b411b8c41c90cf6ba16ed
DIFF:
https://github.com/llvm/llvm-project/commit/0c04af9c9748947bf65b411b8c41c90cf6ba16ed.diff
LOG
https://github.com/qinkunbao created
https://github.com/llvm/llvm-project/pull/142456
See https://github.com/llvm/llvm-project/issues/139128
If multiple entries match the source, than the latest entry takes the
precedence.`
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https://github.com/inbelic updated
https://github.com/llvm/llvm-project/pull/140962
>From bcc056ea5c753c3b1fa83d214c6bd14e90d9ee25 Mon Sep 17 00:00:00 2001
From: Finn Plummer
Date: Wed, 21 May 2025 00:12:04 +
Subject: [PATCH 1/4] [HLSL][RootSignature] Plug into the thing
---
.../clang/Bas
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (llvmbot)
Changes
Backport 3b4c51bb3243a02526313c51207a674139b67a00
Requested by: @anutosh491
---
Full diff: https://github.com/llvm/llvm-project/pull/142445.diff
2 Files Affected:
- (modified) clang/lib/Interpreter/IncrementalPar
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llvmbot wrote:
@vgvassilev What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/142445
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/142445
Backport 3b4c51bb3243a02526313c51207a674139b67a00
Requested by: @anutosh491
>From 4c50edbf427a7ebac4d5a9bf8249203bb112c1a7 Mon Sep 17 00:00:00 2001
From: Anutosh Bhat
Date: Mon, 2 Jun 2025 20:14:28 +0530
Subje
@@ -621,10 +687,10 @@ define i64 @test_resign_da_constdisc(i64 %arg, i64 %arg1)
{
; CHECKED-NEXT:mov x17, x16
; CHECKED-NEXT:xpacd x17
; CHECKED-NEXT:cmp x16, x17
-; CHECKED-NEXT:b.eq [[L]]auth_success_7
+; CHECKED-NEXT:b.eq [[L]]auth_success_[[N1:[0-9]+]]
@@ -1866,7 +1871,6 @@ Register
AArch64AsmPrinter::emitPtrauthDiscriminator(uint16_t Disc,
Register AddrDisc,
Register ScratchReg,
@@ -2064,8 +2069,12 @@ void
AArch64AsmPrinter::emitPtrauthTailCallHardening(const MachineInstr *TC) {
/*ShouldTrap=*/true, /*OnFailure=*/nullptr);
}
-void AArch64AsmPrinter::emitPtrauthAuthResign(const MachineInstr *MI) {
- const bool IsAUTPAC = MI->getOpcode() == AArc
@@ -140,16 +157,18 @@ define i64 @test_resign_blend_and_const(i64 %arg, i64
%arg1) {
; CHECKED-LABEL: test_resign_blend_and_const:
; CHECKED: %bb.0:
; CHECKED-NEXT:mov x16, x0
-; CHECKED-NEXT:mov x17, x1
-; CHECKED-NEXT:movk x17, #12345, lsl #48
-; CHECKED-NE
@@ -168,7 +168,12 @@ class AArch64AsmPrinter : public AsmPrinter {
void emitPtrauthTailCallHardening(const MachineInstr *TC);
// Emit the sequence for AUT or AUTPAC.
- void emitPtrauthAuthResign(const MachineInstr *MI);
+ void emitPtrauthAuthResign(Register AUTVal, AArch
@@ -1951,9 +1952,23 @@ let Predicates = [HasPAuth] in {
let Uses = [X16];
}
+ def AUTxMxN : Pseudo<(outs GPR64:$AuthVal, GPR64common:$Scratch),
+ (ins GPR64:$Val, i32imm:$Key,
+i64imm:$Disc, GPR64:$AddrDisc),
+
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https://github.com/atrosinenko commented:
@pcc Thank you for the updates!
By the way, have you considered splitting `emitPtrauthAuthResign` into "auth"
and "resign" parts? On one hand, this could decrease the number of arguments
passed to a single function. On the other hand, passing "on_succe
Author: cor3ntin
Date: 2025-06-02T18:58:25+02:00
New Revision: 1ccec5e96b2ec873e5a6da60eb9036cf00a94414
URL:
https://github.com/llvm/llvm-project/commit/1ccec5e96b2ec873e5a6da60eb9036cf00a94414
DIFF:
https://github.com/llvm/llvm-project/commit/1ccec5e96b2ec873e5a6da60eb9036cf00a94414.diff
LOG:
llvmbot wrote:
@llvm/pr-subscribers-mlir
@llvm/pr-subscribers-mlir-vector
Author: Momchil Velikov (momchil-velikov)
Changes
Previously, slices were sometimes marked as non-contiguous when they were
actually contiguous. This occurred when the vector type had leading unit
dimensions, e.g.,
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/142422
Previously, slices were sometimes marked as non-contiguous when they were
actually contiguous. This occurred when the vector type had leading unit
dimensions, e.g., `vector<1x1x...x1xd0xd1x...xdn-1xT>`.
MacDue wrote:
This is a stacked PR. See previous PRs below:
1. https://github.com/llvm/llvm-project/pull/142390
2. https://github.com/llvm/llvm-project/pull/142391
3. :point_right: https://github.com/llvm/llvm-project/pull/142392
https://github.com/llvm/llvm-project/pull/142392
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@@ -1904,6 +1904,20 @@ def atomic_load_64 :
let MemoryVT = i64;
}
+def atomic_load_128_v2i64 :
+ PatFrag<(ops node:$ptr),
+ (atomic_load node:$ptr)> {
+ let IsAtomic = true;
+ let MemoryVT = v2i64;
+}
+
+def atomic_load_128_v4i32 :
+ PatFrag<(ops node:$ptr),
+
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Benjamin Maxwell (MacDue)
Changes
For a while we have supported the `-aarch64-stack-hazard-size=`
option, which adds "hazard padding" between GPRs and FPR/ZPRs. However, there
is currently a hole in this mitigation as PPR
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Benjamin Maxwell (MacDue)
Changes
This patch attempts to refactor AArch64FrameLowering to allow the size of the
ZPR and PPR areas to be calculated separately. This will be used by a
subsequent patch to support allocating ZPRs an
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MacDue wrote:
This is a stacked PR. Please see the final PR for context.
1. https://github.com/llvm/llvm-project/pull/142390
2. :point_right: https://github.com/llvm/llvm-project/pull/142391
3. https://github.com/llvm/llvm-project/pull/142392
https://github.com/llvm/llvm-project/pull/142391
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https://github.com/MacDue created
https://github.com/llvm/llvm-project/pull/142391
This patch attempts to refactor AArch64FrameLowering to allow the size of the
ZPR and PPR areas to be calculated separately. This will be used by a
subsequent patch to support allocating ZPRs and PPRs to separat
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@@ -285,6 +285,9 @@ bool hasDynamicSize(mlir::Type t) {
return true;
if (auto rec = mlir::dyn_cast(t))
return hasDynamicSize(rec);
+ if (auto boxChar = mlir::dyn_cast(t)) {
+return characterWithDynamicLen(boxChar.getEleTy());
+ }
jeanPerier wrot
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@@ -32070,6 +32070,13 @@
X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
}
}
+TargetLowering::AtomicExpansionKind
+X86TargetLowering::shouldCastAtomicLoadInIR(LoadInst *LI) const {
+ if (LI->getType()->getScalarType()->isFloatingPointTy())
+retu
@@ -1211,6 +1211,11 @@ def : Pat<(v4i32 (scalar_to_vector (i32 (atomic_load_32
addr:$src,
def : Pat<(v2i64 (scalar_to_vector (i64 (atomic_load_64 addr:$src,
(MOV64toPQIrm addr:$src)>; // load atomic <2 x i32,float>
+def : Pat<(v2i64 (atomic_load_128_v2i64
@@ -6003,6 +6006,74 @@ SDValue
DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
N->getOperand(1), N->getOperand(2));
}
+/// Either return the same load or provide appropriate casts
+/// from the load and return that.
+static SDValue coerceLoad
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@@ -1211,6 +1211,11 @@ def : Pat<(v4i32 (scalar_to_vector (i32 (atomic_load_32
addr:$src,
def : Pat<(v2i64 (scalar_to_vector (i64 (atomic_load_64 addr:$src,
(MOV64toPQIrm addr:$src)>; // load atomic <2 x i32,float>
+def : Pat<(v2i64 (atomic_load_128_v2i64
@@ -1904,6 +1904,20 @@ def atomic_load_64 :
let MemoryVT = i64;
}
+def atomic_load_128_v2i64 :
+ PatFrag<(ops node:$ptr),
+ (atomic_load node:$ptr)> {
+ let IsAtomic = true;
+ let MemoryVT = v2i64;
+}
+
+def atomic_load_128_v4i32 :
+ PatFrag<(ops node:$ptr),
+
https://github.com/nikic approved this pull request.
https://github.com/llvm/llvm-project/pull/142311
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@@ -741,8 +743,8 @@ GCNTTIImpl::getIntrinsicInstrCost(const
IntrinsicCostAttributes &ICA,
case Intrinsic::copysign:
return NElts * getFullRateInstrCost();
case Intrinsic::canonicalize: {
-assert(SLT != MVT::f64);
-InstRate = getFullRateInstrCost();
+InstRat
@@ -741,8 +743,8 @@ GCNTTIImpl::getIntrinsicInstrCost(const
IntrinsicCostAttributes &ICA,
case Intrinsic::copysign:
return NElts * getFullRateInstrCost();
case Intrinsic::canonicalize: {
-assert(SLT != MVT::f64);
-InstRate = getFullRateInstrCost();
+InstRat
https://github.com/Pierre-vh edited
https://github.com/llvm/llvm-project/pull/141945
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https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/141946
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https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/141904
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@@ -281,6 +281,13 @@ class GCNTTIImpl final : public
BasicTTIImplBase {
void collectKernelLaunchBounds(
const Function &F,
SmallVectorImpl> &LB) const override;
+
+ enum class KnownIEEEMode { Unknown, On, Off };
+
+ /// Return KnownIEEEMode::On if we know if th
https://github.com/Pierre-vh approved this pull request.
unrelated to this patch but `KnownIEEEMode::Unknown` looks weird, maybe it
should just be named `IEEEMode`?
https://github.com/llvm/llvm-project/pull/141945
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@@ -742,6 +744,23 @@ GCNTTIImpl::getIntrinsicInstrCost(const
IntrinsicCostAttributes &ICA,
break;
case Intrinsic::copysign:
return NElts * getFullRateInstrCost();
+ case Intrinsic::minimumnum:
+ case Intrinsic::maximumnum: {
+// Instruction + 2 canonicalizes. F
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