el-ev wrote:
Graphite is somewhat dumb here as it can't retarget one pr onto another. The
scheduler definition will be added later, once either this PR or #139495 is
merged.
https://github.com/llvm/llvm-project/pull/139508
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https://github.com/maksfb approved this pull request.
https://github.com/llvm/llvm-project/pull/139194
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https://github.com/maksfb approved this pull request.
https://github.com/llvm/llvm-project/pull/139337
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https://github.com/llvm/llvm-project/pull/139495
>From 4fe33b2443138357709c890023abc8ba4d974ab7 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
>From e8c188a0ea28030c01af913f9cc4eb57e9224a9c Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa
---
llvm/lib/Target/RI
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
>From e8c188a0ea28030c01af913f9cc4eb57e9224a9c Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa
---
llvm/lib/Target/RI
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From a3dd59810a7b20bfc941d5723b8f4e9a1619234a Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From a3dd59810a7b20bfc941d5723b8f4e9a1619234a Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 4fe33b2443138357709c890023abc8ba4d974ab7 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
ex
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
>From 1a1cb30959da66d02bf64927ca7fcc5f8de290dc Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa
---
llvm/lib/Target/RI
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139508
>From 1a1cb30959da66d02bf64927ca7fcc5f8de290dc Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa
---
llvm/lib/Target/RI
aaupov wrote:
> The code LGTM.
>
> For practical applications, we sometimes use 3-way function splitting
> resulting in code being broken into more than two partitions. In such case,
> the most interesting metrics and score should be attached to non-cold
> partitions. With "hot text" enabled,
https://github.com/maksfb approved this pull request.
The code LGTM.
For practical applications, we sometimes use 3-way function splitting resulting
in code being broken into more than two partitions. In such case, the most
interesting metrics and score should be attached to non-cold partition
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133535
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pcc wrote:
I've now implemented the ADDRINIT64 (renamed FUNCINIT64, but no strong opinions
on the name) proposal as well as filed an issue with the AArch64 psABI:
https://github.com/ARM-software/abi-aa/issues/329
https://github.com/llvm/llvm-project/pull/133531
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/133538
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>From 96e7da9a083888683c2ba00d97f886fd748ea10b Mon Sep 17 00:00:00 2001
From: Peter Collingbourne
Date: Wed, 9 Apr 2025 20:30:57 -0700
Subject: [PATCH] Undo unnecessary change
Created using spr 1.3.6-beta.1
---
lld
https://github.com/pcc edited https://github.com/llvm/llvm-project/pull/133532
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>From 4e26ed5b43593bdc7dbac86557e9ff2ba0c85fa7 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Wed, 30 Apr 2025 08:10:20 -0700
Subject: [PATCH] [clang-doc] Add helpers for Template config
This patch adds or fil
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$r
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/138798
>From f6b275f682c598d5c026efcbd348c6e8a35c759b Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Tue, 6 May 2025 20:09:58 -0700
Subject: [PATCH 1/2] keep parsing build-id
Created using spr 1.3.4
---
bolt/lib/Pro
https://github.com/aaupov updated
https://github.com/llvm/llvm-project/pull/138798
>From f6b275f682c598d5c026efcbd348c6e8a35c759b Mon Sep 17 00:00:00 2001
From: Amir Ayupov
Date: Tue, 6 May 2025 20:09:58 -0700
Subject: [PATCH 1/2] keep parsing build-id
Created using spr 1.3.4
---
bolt/lib/Pro
https://github.com/maksfb approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/138798
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@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$r
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$r
@@ -55,11 +55,33 @@ export void foo() {
// CHECK-SAME: i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3)
// CHECK-NEXT: ret void
-// Buf2 initialization part 1 - FIXME: constructor with implicit binding does
not exist yet;
-// the global init function currently
@@ -3269,27 +3285,42 @@ static bool initVarDeclWithCtor(Sema &S, VarDecl *VD,
return true;
}
-static bool initGlobalResourceDecl(Sema &S, VarDecl *VD) {
+bool SemaHLSL::initGlobalResourceDecl(VarDecl *VD) {
+ std::optional RegisterSlot;
+ uint32_t SpaceNo = 0;
HLSLResou
https://github.com/V-FEXrt approved this pull request.
https://github.com/llvm/llvm-project/pull/138976
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@@ -668,6 +668,26 @@ BuiltinTypeDeclBuilder::addHandleConstructorFromBinding() {
.finalize();
}
+BuiltinTypeDeclBuilder &
+BuiltinTypeDeclBuilder::addHandleConstructorFromImplicitBinding() {
+ if (Record->isCompleteDefinition())
V-FEXrt wrote:
Could yo
@@ -668,6 +668,26 @@ BuiltinTypeDeclBuilder::addHandleConstructorFromBinding() {
.finalize();
}
+BuiltinTypeDeclBuilder &
+BuiltinTypeDeclBuilder::addHandleConstructorFromImplicitBinding() {
+ if (Record->isCompleteDefinition())
+return *this;
+
+ using PH = Builti
@@ -7970,17 +7970,26 @@ void SelectionDAGBuilder::visitIntrinsicCall(const
CallInst &I,
// On arm64_32, pointers are 32 bits when stored in memory, but
// zero-extended to 64 bits when in registers. Thus the mask is 32 bits to
-// match the index type, but the po
https://github.com/hekota edited
https://github.com/llvm/llvm-project/pull/139022
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arsenm wrote:
> Of the 128-bits of buffer descriptor only 48 bits are address bits,
Technically true, but why not just call it 64?
https://github.com/llvm/llvm-project/pull/139419
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>From 25dc175562349410f161ef0e80246301d9a7ba79 Mon Sep 17 00:00:00 2001
From: Alex Richardson
Date: Fri, 9 May 2025 22:43:37 -0700
Subject: [PATCH] fix docs build
Created using spr 1.3.6-beta.1
---
llvm/do
https://github.com/arichardson updated
https://github.com/llvm/llvm-project/pull/139357
>From 25dc175562349410f161ef0e80246301d9a7ba79 Mon Sep 17 00:00:00 2001
From: Alex Richardson
Date: Fri, 9 May 2025 22:43:37 -0700
Subject: [PATCH] fix docs build
Created using spr 1.3.6-beta.1
---
llvm/do
https://github.com/vitalybuka approved this pull request.
https://github.com/llvm/llvm-project/pull/139389
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@@ -5773,7 +5773,7 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL,
StringRef TT) {
if (!DL.contains("-p7") && !DL.starts_with("p7"))
Res.append("-p7:160:256:256:32");
if (!DL.contains("-p8") && !DL.starts_with("p8"))
- Res.append("-p8:128:128");
+
arichardson wrote:
Now that we use the full bitwidth the high KnownBits are no longer zext'ed to
zeroes. But maybe the better approahc would be to just do KnownBits on the
address bits and set the high bits to unknown?
That should fix the issue as well?
https://github.com/llvm/llvm-project/pu
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Alexander Richardson (arichardson)
Changes
While we can only reason about the index/address, the G_PTRTOINT
operations returns all representation bits, so we can't assume the
remaining ones are all zeroes.
This behaviour was clarif
https://github.com/arichardson created
https://github.com/llvm/llvm-project/pull/139608
While we can only reason about the index/address, the G_PTRTOINT
operations returns all representation bits, so we can't assume the
remaining ones are all zeroes.
This behaviour was clarified as part of the d
https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/139022
>From 8194951b52e024b78c7f148d65ce6c23b3fcf424 Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Wed, 7 May 2025 21:05:39 -0700
Subject: [PATCH 1/6] [HLSL] Implicit binding for cbuffers
Constant buffers defined
@@ -0,0 +1,200 @@
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,debug.ExprInspection
-verify=expected,default %s
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,debug.ExprInspection
-analyzer-config inline-functions-with-ambiguous-loops=true
-verify=expected,enabled %s
@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const
User &U,
return true;
}
+bool IRTranslator::translatePtrToAddr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
+ if (containsBF16Type(U))
+return false;
@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const
User &U,
return true;
}
+bool IRTranslator::translatePtrToAddr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
+ if (containsBF16Type(U))
+return false;
@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const
User &U,
return true;
}
+bool IRTranslator::translatePtrToAddr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
+ if (containsBF16Type(U))
+return false;
@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const
User &U,
return true;
}
+bool IRTranslator::translatePtrToAddr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
+ if (containsBF16Type(U))
+return false;
@@ -5773,7 +5773,7 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL,
StringRef TT) {
if (!DL.contains("-p7") && !DL.starts_with("p7"))
Res.append("-p7:160:256:256:32");
if (!DL.contains("-p8") && !DL.starts_with("p8"))
- Res.append("-p8:128:128");
+
https://github.com/krzysz00 commented:
Minor note re the autoupgrade, overall this change makes sense
(and it does mean that, if we can get GEP's "wrapping add on the index bits"
behavior working, ptr addrspace(8)` becomes *technically* GEPable, though with
the note of "be real hecking careful
https://github.com/krzysz00 edited
https://github.com/llvm/llvm-project/pull/139419
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@@ -145,79 +145,79 @@ define amdgpu_ps ptr addrspace(7)
@s_ptrmask_buffer_fat_ptr_i32_neg8(ptr addrspa
ret ptr addrspace(7) %masked
}
-define ptr addrspace(8) @v_ptrmask_buffer_resource_variable_i128(ptr
addrspace(8) %ptr, i128 %mask) {
-; GCN-LABEL: v_ptrmask_buffer_resou
@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const
User &U,
return true;
}
+bool IRTranslator::translatePtrToAddr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
+ if (containsBF16Type(U))
+return false;
@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const
User &U,
return true;
}
+bool IRTranslator::translatePtrToAddr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
+ if (containsBF16Type(U))
+return false;
@@ -1583,6 +1583,26 @@ bool IRTranslator::translateCast(unsigned Opcode, const
User &U,
return true;
}
+bool IRTranslator::translatePtrToAddr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
+ if (containsBF16Type(U))
+return false;
@@ -1952,6 +1953,22 @@ PtrParts SplitPtrStructs::visitPtrToIntInst(PtrToIntInst
&PI) {
return {nullptr, nullptr};
}
+PtrParts SplitPtrStructs::visitPtrToAddrInst(PtrToAddrInst &PA) {
+ Value *Ptr = PA.getPointerOperand();
+ if (!isSplitFatPtr(Ptr->getType()))
+return
https://github.com/krzysz00 approved this pull request.
One tiny nit, lgtm otherwise
https://github.com/llvm/llvm-project/pull/139413
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llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
Author: Alexander Richardson (arichardson)
Changes
We lower ptrtoaddr by emitting a G_PTRTOINT, truncating that to the
address size and then truncate/zext to the final integer type.
This has exposed an issue in the GlobalIsel postlegaliz
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Alexander Richardson (arichardson)
Changes
We lower ptrtoaddr by emitting a G_PTRTOINT, truncating that to the
address size and then truncate/zext to the final integer type.
This has exposed an issue in the GlobalIsel postlegalize
https://github.com/arichardson created
https://github.com/llvm/llvm-project/pull/139601
We lower ptrtoaddr by emitting a G_PTRTOINT, truncating that to the
address size and then truncate/zext to the final integer type.
This has exposed an issue in the GlobalIsel postlegalizer combines where
the
arsenm wrote:
### Merge activity
* **May 12, 2:11 PM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/139530).
https://github.com/llvm/llvm-project/pull/139530
_
arsenm wrote:
### Merge activity
* **May 12, 2:11 PM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/139531).
https://github.com/llvm/llvm-project/pull/139531
_
@@ -0,0 +1,200 @@
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,debug.ExprInspection
-verify=expected,default %s
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,debug.ExprInspection
-analyzer-config inline-functions-with-ambiguous-loops=true
-verify=expected,enabled %s
https://github.com/NagyDonat commented:
I read this rebased code and IMO it should work -- however I found a whitespace
error that originated in my commit :sweat_smile:
https://github.com/llvm/llvm-project/pull/139597
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https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/139508
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llvmbot wrote:
@llvm/pr-subscribers-clang-static-analyzer-1
Author: Balazs Benics (steakhal)
Changes
Recently some users reported that they observed large increases of runtime (up
to +600% on some translation units) when they upgraded to a more recent
(slightly patched, internal) clang v
steakhal wrote:
This is a manual backport of #136720.
https://github.com/llvm/llvm-project/pull/139597
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https://github.com/steakhal created
https://github.com/llvm/llvm-project/pull/139597
Recently some users reported that they observed large increases of runtime (up
to +600% on some translation units) when they upgraded to a more recent
(slightly patched, internal) clang version. Bisection reve
https://github.com/steakhal milestoned
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steakhal wrote:
We decided to backport in
https://github.com/llvm/llvm-project/pull/127406#issuecomment-2683679225
https://github.com/llvm/llvm-project/pull/139591
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llvmbot wrote:
@llvm/pr-subscribers-clang-analysis
Author: Balazs Benics (steakhal)
Changes
In my previous attempt (#126913) of fixing the flaky case was on a good
track when I used the begin locations as a stable ordering. However, I forgot
to consider the case when the begin locations
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Balazs Benics (steakhal)
Changes
In my previous attempt (#126913) of fixing the flaky case was on a good
track when I used the begin locations as a stable ordering. However, I forgot
to consider the case when the begin locations are the s
https://github.com/steakhal milestoned
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https://github.com/steakhal created
https://github.com/llvm/llvm-project/pull/139591
In my previous attempt (#126913) of fixing the flaky case was on a good track
when I used the begin locations as a stable ordering. However, I forgot to
consider the case when the begin locations are the same
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/139531
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