Author: slthakur
Date: Thu Oct 1 10:05:31 2015
New Revision: 249020
URL: http://llvm.org/viewvc/llvm-project?rev=249020&view=rev
Log:
[LLDB][MIPS] Fix gp register value for o32 applications on 64-bit target
GP registers for o32 applications were always giving zero value because
SetType() on the
Author: slthakur
Date: Thu Oct 1 10:15:42 2015
New Revision: 249021
URL: http://llvm.org/viewvc/llvm-project?rev=249021&view=rev
Log:
Romove accidentially added statement in r249020
Modified:
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
Modified: lldb/trunk/source/Plugins/Obje
Author: slthakur
Date: Mon Oct 19 06:21:20 2015
New Revision: 250696
URL: http://llvm.org/viewvc/llvm-project?rev=250696&view=rev
Log:
[LLDB][MIPS] Use the correct ptrace buffer for writing register value for o32
applications
For o32 applications on mips we were getting segmentation fault while
sagar created this revision.
sagar added reviewers: clayborg, tberghammer.
sagar added subscribers: nitesh.jain, jaydeep, bhushan, mohit.bhakkad,
lldb-commits.
sagar set the repository for this revision to rL LLVM.
Herald added a subscriber: dsanders.
This patch will clear bug 25194 - LLDB-Server
sagar updated this revision to Diff 40256.
sagar added a comment.
Addressed review comments.
Repository:
rL LLVM
http://reviews.llvm.org/D14633
Files:
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.c
sagar added a comment.
> Admittedly it's a bit unintuitive for an unsigned 32-bit value from a MIPS32
> binary to be represented in a 64-bit register as, for example,
> 0x8000 but the debugger shouldn't normally admit to the existence
> of the extra bits when debugging 32-bit code s
sagar added a comment.
Hi @tberghammer,
I tried using RegisterValue::SetUInt() instead of RegisterValue::SetBytes().
When using RegisterValue::SetUInt() all register values we get are zero in case
of mips32 big endian machine. The
GDBRemoteCommunicationServerLLGS::SendStopReplyPacketForThread(
Author: slthakur
Date: Wed Nov 18 02:12:34 2015
New Revision: 253444
URL: http://llvm.org/viewvc/llvm-project?rev=253444&view=rev
Log:
[MIPS][LLDB]Fix TestBreakpointCondition.py for MIPS
Patch by Nitesh Jain
Summary: The self.getArchitecture() returns the architecture based on the value
of -A f
sagar closed this revision.
sagar added a comment.
Committed in r253444 on behalf of @nitesh.jain
Repository:
rL LLVM
http://reviews.llvm.org/D14493
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Author: slthakur
Date: Wed Nov 18 02:18:03 2015
New Revision: 253445
URL: http://llvm.org/viewvc/llvm-project?rev=253445&view=rev
Log:
[LLDB][MIPS] Fix TestDisassembleBreakpoint.py for MIPS
Patch by Nitesh Jain
Summary: The break is opcode for breakpoint instruction.
Subscribers: lldb-commits,
sagar added a comment.
Committed in r253445 on behalf of @nitesh.jain
Repository:
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http://reviews.llvm.org/D14634
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sagar added a comment.
Hi,
@tberghammer : For both mips32 and mips64 big endian 'T' packet response
contains the register values in target byte order only. But for mips32 big
endian when we set the value of the register in RegisterValue using
RegisterValue::SetUInt() the upper half of the cont
Author: slthakur
Date: Thu Nov 19 05:01:21 2015
New Revision: 253555
URL: http://llvm.org/viewvc/llvm-project?rev=253555&view=rev
Log:
[LLDB][MIPS] Fix lldbplatformutil.py Failure
Patch by Nitesh Jain
Summary: This patch check whether first register is readable.
Subscribers: lldb-commits, mohit
sagar closed this revision.
sagar added a comment.
Committed in r253555 on behalf of @nitesh.jain
Repository:
rL LLVM
http://reviews.llvm.org/D14635
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sagar added a comment.
Hi,
Could we use SetBytes for now for clearing the bug 25194? I have tried using
SetBytes(), it does not cause any issue on MIPS for both endian. Once we have a
new function to llvm::APInt to access actual data I will revert back to using
SetUInt. Kindly let me know if y
sagar updated this revision to Diff 41232.
sagar added a comment.
Addressed review comments
Repository:
rL LLVM
http://reviews.llvm.org/D14633
Files:
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cp
Author: slthakur
Date: Mon Nov 30 23:44:18 2015
New Revision: 254379
URL: http://llvm.org/viewvc/llvm-project?rev=254379&view=rev
Log:
[LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single
stepping on MIPS
This patch will clear bug 25194 - LLDB-Server Assertion raised when sing
sagar closed this revision.
sagar added a comment.
Committed in revision 254379
Repository:
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http://reviews.llvm.org/D14633
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Author: slthakur
Date: Sat Dec 5 06:01:48 2015
New Revision: 254850
URL: http://llvm.org/viewvc/llvm-project?rev=254850&view=rev
Log:
[LLDB][MIPS] Fix TestConstVariables.py
Patch by Nitesh Jain.
Summary: There is no debug information generated for variable index with –O3
optimization flag. The
sagar closed this revision.
sagar added a comment.
Committed in revision 254850 on behalf of Nitesh Jain.
Repository:
rL LLVM
http://reviews.llvm.org/D15224
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Author: slthakur
Date: Wed Dec 9 06:31:01 2015
New Revision: 255108
URL: http://llvm.org/viewvc/llvm-project?rev=255108&view=rev
Log:
[LLDB][MIPS] Adding call to IsMSAAvailable() while creating
RegisterInfoInterface
This patch will fix the test case
test_p_returns_correct_data_size_for_each_qR
Author: slthakur
Date: Wed May 11 08:08:29 2016
New Revision: 269181
URL: http://llvm.org/viewvc/llvm-project?rev=269181&view=rev
Log:
[LLDB][MIPS] Setting appropriate ArchSpec::m_flags based on ABI
Patch by Nitesh Jain.
Summary: The ArchSpec::m_flags will be set based on ELF flag ABI.
Reviewer
Author: slthakur
Date: Fri May 13 06:04:47 2016
New Revision: 269407
URL: http://llvm.org/viewvc/llvm-project?rev=269407&view=rev
Log:
[LLDB][MIPS] Provide ABI string to compiler for appropriate code generation for
MIPS
Patch by Nitesh Jain.
Summary: These patch will set clang::TargetOptions::A
Author: slthakur
Date: Fri May 20 07:07:27 2016
New Revision: 270207
URL: http://llvm.org/viewvc/llvm-project?rev=270207&view=rev
Log:
[LLDB][MIPS] Fix floating point handling in case of thread step-out
Patch by Nitesh Jain.
Summary: These patch fix thread step-out for hard and soft float.
Revi
Author: slthakur
Date: Fri May 20 07:11:52 2016
New Revision: 270208
URL: http://llvm.org/viewvc/llvm-project?rev=270208&view=rev
Log:
[LLDB][MIPS] Fix Floating point Registers Encoding
Patch by Nitesh Jain.
Summary: Currently floating point regsiters has eEncodingUint encoding. Hence
register
Author: slthakur
Date: Tue May 24 09:52:50 2016
New Revision: 270564
URL: http://llvm.org/viewvc/llvm-project?rev=270564&view=rev
Log:
[LLDB][MIPS] Fix floating point handling in case of thread step-out
Patch by Nitesh Jain.
Summary: These patch fix thread step-out for hard and soft float.
Revi
This revision was automatically updated to reflect the committed changes.
Closed by commit rL270564: [LLDB][MIPS] Fix floating point handling in case of
thread step-out (authored by slthakur).
Changed prior to commit:
http://reviews.llvm.org/D20416?vs=57739&id=58236#toc
Repository:
rL LLVM
Author: slthakur
Date: Thu Jun 23 01:40:37 2016
New Revision: 273535
URL: http://llvm.org/viewvc/llvm-project?rev=273535&view=rev
Log:
[LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructions
Patch by Nitesh Jain.
This patch contains 2 changes:
- Corrected target address calculatio
slthakur closed this revision.
slthakur added a comment.
Committed in http://reviews.llvm.org/rL273535
Repository:
rL LLVM
http://reviews.llvm.org/D21064
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Author: slthakur
Date: Wed Jun 29 07:30:18 2016
New Revision: 274121
URL: http://llvm.org/viewvc/llvm-project?rev=274121&view=rev
Log:
[LLDB][MIPS] Check if libatomic needs to be specified explicitly
Patch by Nitesh Jain.
Summary : The problem appears while linking liblldb.so. The class Address
Author: slthakur
Date: Mon Dec 14 23:50:55 2015
New Revision: 255619
URL: http://llvm.org/viewvc/llvm-project?rev=255619&view=rev
Log:
[LLDB][MIPS] Added support for MIPS1, MIPS2, MIPS3, MIPS4 and MIPS5 instruction
sets
Patch by Nitesh Jain.
Summary: This Patch will allowed LLDB to debug respec
sagar closed this revision.
sagar added a comment.
Committed in revision 255619 on behalf of Nitesh Jain.
Repository:
rL LLVM
http://reviews.llvm.org/D15487
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sagar created this revision.
sagar added reviewers: clayborg, tberghammer.
sagar added subscribers: jaydeep, bhushan, mohit.bhakkad, nitesh.jain,
lldb-commits.
sagar set the repository for this revision to rL LLVM.
For O32 abi register size should be 4 bytes.
For N32 and N64 abi register size sho
Author: slthakur
Date: Tue Jan 5 08:03:45 2016
New Revision: 256834
URL: http://llvm.org/viewvc/llvm-project?rev=256834&view=rev
Log:
[LLDB][MIPS] Make register read/write to set/get the size of register according
to abi.
Summary:
For O32 abi register size should be 4 bytes.
For N32 and N64 abi
sagar closed this revision.
sagar marked an inline comment as done.
sagar added a comment.
Committed in revision 256834
Repository:
rL LLVM
http://reviews.llvm.org/D15884
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Author: slthakur
Date: Wed Jan 13 05:22:56 2016
New Revision: 257587
URL: http://llvm.org/viewvc/llvm-project?rev=257587&view=rev
Log:
[LLDB][MIPS] Fix TestDisassembleRawData.py
Patch by Nitesh Jain.
Summary: This patch adds check for the correctness of disassembling instruction
for MIPS target
sagar closed this revision.
sagar added a comment.
Committed in revision 257587 on behalf of Nitesh Jain.
Repository:
rL LLVM
http://reviews.llvm.org/D15915
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Author: slthakur
Date: Mon Jan 25 06:27:46 2016
New Revision: 258684
URL: http://llvm.org/viewvc/llvm-project?rev=258684&view=rev
Log:
[LLDB][MIPS] Fix TestExprsChar.py
Patch by Nitesh Jain.
Summary: When incorrect type used for 'char' then (at least) one of the
expression evaluates to incorrec
sagar closed this revision.
sagar added a comment.
Committed in revision 258684
Repository:
rL LLVM
http://reviews.llvm.org/D16132
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Author: slthakur
Date: Mon Jan 25 06:33:03 2016
New Revision: 258685
URL: http://llvm.org/viewvc/llvm-project?rev=258685&view=rev
Log:
[LLDB][MIPS] Fix TestPrintStackTraces.py
Patch by Nitesh Jain.
Summary: The thread_start function in libc doesn't contain any epilogue and
prologue instructions
sagar closed this revision.
sagar added a comment.
Committed in revision 258685.
Repository:
rL LLVM
http://reviews.llvm.org/D16136
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Author: slthakur
Date: Fri Feb 26 07:30:34 2016
New Revision: 262011
URL: http://llvm.org/viewvc/llvm-project?rev=262011&view=rev
Log:
[LLDB][MIPS] Fix TestInferiorAssert.py for MIPS
Patch by Nitesh Jain.
Summary: The debug version of libc.so is require for backtracing which may not
be availabl
sagar closed this revision.
sagar added a comment.
Committed in revision 262011.
Repository:
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http://reviews.llvm.org/D17131
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sagar accepted this revision.
sagar added a comment.
This revision is now accepted and ready to land.
LGTM
Repository:
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http://reviews.llvm.org/D18853
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sagar added a comment.
Hi,
I have corrected the patch for Scalar which was reverted in r245222 and
addressed all concerns raised (http://reviews.llvm.org/rL245216) by Pavel
Labath.
Could you please review it?
Repository:
rL LLVM
http://reviews.llvm.org/D12100
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sagar added inline comments.
Comment at: include/lldb/Core/RegisterValue.h:185
@@ -190,1 +184,3 @@
+llvm::APInt
+GetAsUInt128 (llvm::APInt& fail_value, bool *success_ptr = NULL) const;
ovyalov wrote:
> Could you pass fail_value as a const referen
Author: slthakur
Date: Tue Aug 25 04:52:59 2015
New Revision: 245927
URL: http://llvm.org/viewvc/llvm-project?rev=245927&view=rev
Log:
Fix build on mips
Setting and getting register values as bytes instead of depending on the 128
bit integer support in register value.
This patch will fix the bui
sagar added a comment.
Hi Hans,
I have committed it to the trunk in revision 245927. You can now merge it to
the release branch.
Thanks,
Sagar
Repository:
rL LLVM
http://reviews.llvm.org/D12275
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sagar created this revision.
sagar added reviewers: jaydeep, clayborg.
sagar added subscribers: bhushan, mohit.bhakkad, nitesh.jain, lldb-commits.
sagar set the repository for this revision to rL LLVM.
This patch adds MSA branch instruction emulation for MIPS64.
Repository:
rL LLVM
http://revi
sagar updated this revision to Diff 33323.
sagar added a comment.
Addressed review comments
Repository:
rL LLVM
http://reviews.llvm.org/D12356
Files:
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
Index: source
sagar updated this revision to Diff 33567.
sagar added a comment.
Addressed review commenst
Repository:
rL LLVM
http://reviews.llvm.org/D12356
Files:
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
Index: source
sagar marked 7 inline comments as done.
Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3160
@@ +3159,3 @@
+if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) )
+branch_hit = false;
+break;
T
sagar updated this revision to Diff 33668.
sagar marked 4 inline comments as done.
sagar added a comment.
Corrected code indent and initialized wr_val correctly.
Repository:
rL LLVM
http://reviews.llvm.org/D12356
Files:
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
sourc
Author: slthakur
Date: Wed Sep 2 22:57:44 2015
New Revision: 246745
URL: http://llvm.org/viewvc/llvm-project?rev=246745&view=rev
Log:
[MIPS64] Emulate MSA branch instructions
This patch adds MSA branch instruction emulation for MIPS64.
Reviewers: tberghammer, jaydeep
Subscribers: tberghammer, l
sagar closed this revision.
sagar added a comment.
Committed in revision 246745
Repository:
rL LLVM
http://reviews.llvm.org/D12356
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Author: slthakur
Date: Tue Sep 22 08:57:11 2015
New Revision: 248277
URL: http://llvm.org/viewvc/llvm-project?rev=248277&view=rev
Log:
[MIPS32] Emulate MSA instructions for MIPS32
This patch adds MSA branch instruction emulation for MIPS32.
Reviewers: tberghammer, jaydeep
Subscribers: mohit.bhak
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