nitesh.jain created this revision.
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This patch add fix for reading and writing floating point register based on
SR.FR bit.
https://reviews.l
nitesh.jain added inline comments.
Comment at:
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp:1183
@@ +1182,3 @@
+ case dwarf_config5_mips64:
+return reg_info->byte_offset;
+ case dwarf_cause_mips:
labath wrote:
> Why do we need to do th
nitesh.jain updated this revision to Diff 71505.
nitesh.jain added a comment.
Updated diff as per suggestion.
https://reviews.llvm.org/D24603
Files:
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
Index: so
nitesh.jain marked an inline comment as done.
nitesh.jain added a comment.
https://reviews.llvm.org/D24603
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nitesh.jain added inline comments.
Comment at:
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp:1183
@@ +1182,3 @@
+ case dwarf_config5_mips64:
+return reg_info->byte_offset;
+ case dwarf_cause_mips:
Changing LLDB numbering scheme is not f
nitesh.jain updated the summary for this revision.
nitesh.jain updated this revision to Diff 72024.
https://reviews.llvm.org/D24124
Files:
source/Core/RegisterValue.cpp
source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux.
nitesh.jain added a comment.
In https://reviews.llvm.org/D24124#543823, @clayborg wrote:
> A few things about a the RegisterContext class in case it would change and
> thing that you are submitting here. The entire register context defines a
> buffer of bytes that can contain all register value
nitesh.jain updated this revision to Diff 72618.
nitesh.jain added a comment.
Herald added a subscriber: ki.stfu.
Updated patch as per suggestion.
https://reviews.llvm.org/D24603
Files:
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
source/Plugins/Process/Linux/NativeReg
nitesh.jain added a comment.
In https://reviews.llvm.org/D24603#548902, @clayborg wrote:
> So it seems like this can be fixed by doing a few things:
> 1 - just set the RegisterInfo.offset to the actual offset in the buffer and
> don't use the offset as the ptrace key used to grab the register
>
nitesh.jain created this revision.
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In case of MIPS64, the pointer size depends on ELF abi. The MIPS64 currently
supp
nitesh.jain added inline comments.
Comment at:
source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp:1218
@@ +1217,3 @@
+response.Printf("eflags:%" PRIx32 ";", proc_arch.GetFlags());
+if (proc_triple.isArch64Bit()) {
+ if (proc_arch.IsMIPS()) {
--
nitesh.jain removed rL LLVM as the repository for this revision.
nitesh.jain updated this revision to Diff 73029.
nitesh.jain added a comment.
We just require ABI information so that auxv vector is parse when lldb try to
attach a process via "attach -p pid"
https://reviews.llvm.org/D25021
File
nitesh.jain updated this revision to Diff 73278.
nitesh.jain added a comment.
These diff remove manually bit twiddling due to the size of the floating point
register that can change. We use register offset to get floating point register
data based on endianess and it's size. We have not remove b
nitesh.jain created this revision.
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This Patch will allowed LLDB to debug respective instruction sets binaries.
R
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This patch adds check for the correctness of Disassembling
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When incorrect type used for 'char' then (at least) one of the expre
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For mips there are more subarchs like mips32r2, mips32r6. This patch uses
re.match("mi
nitesh.jain added a comment.
Thanks zturner.
The triple is match using re.match(triple,
lldb.DBG.GetSelectedPlatform().GetTriple()).
I will update diff with the suggested changes.
Repository:
rL LLVM
http://reviews.llvm.org/D16840
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nitesh.jain updated this revision to Diff 46750.
nitesh.jain added a comment.
Update the diff with suggested changes
Repository:
rL LLVM
http://reviews.llvm.org/D16840
Files:
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py
packages/Python/
nitesh.jain marked an inline comment as done.
Comment at:
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step/TestCrashDuringStep.py:24
@@ -23,3 +23,3 @@
@expectedFailureAndroid("llvm.org/pr24497", archs=['arm', 'aarch64'])
-@expectedFailureAll(archs=
nitesh.jain updated the summary for this revision.
nitesh.jain updated this revision to Diff 46913.
nitesh.jain added a comment.
Updated as per the suggestion.
Repository:
rL LLVM
http://reviews.llvm.org/D16840
Files:
packages/Python/lldbsuite/test/functionalities/thread/crash_during_step
nitesh.jain updated this revision to Diff 46919.
nitesh.jain added a comment.
updates diff with triple =re.compile('^mips') to check if architecture string
starts with mips.
Repository:
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http://reviews.llvm.org/D16840
Files:
packages/Python/lldbsuite/test/functionalities/thread/cr
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The debug version of libc.so is require for backtracing which may n
nitesh.jain updated this revision to Diff 47767.
nitesh.jain added a comment.
Updated as per suggestion.
Repository:
rL LLVM
http://reviews.llvm.org/D17131
Files:
packages/Python/lldbsuite/test/functionalities/inferior-assert/TestInferiorAssert.py
Index:
packages/Python/lldbsuite/test/f
nitesh.jain marked an inline comment as done.
nitesh.jain added a comment.
Thanks zturner.
Will update the diff as per suggestion.
Repository:
rL LLVM
http://reviews.llvm.org/D17131
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nitesh.jain updated this revision to Diff 47776.
nitesh.jain added a comment.
Update the diff as per suggestion.
Repository:
rL LLVM
http://reviews.llvm.org/D17131
Files:
packages/Python/lldbsuite/test/functionalities/inferior-assert/TestInferiorAssert.py
Index:
packages/Python/lldbsuit
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The MIPS/MICROMIPS architecture will generate different jump instruction.
nitesh.jain created this revision.
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The patch http://reviews.llvm.org/D14952 which modifies
nitesh.jain updated this revision to Diff 50569.
nitesh.jain added a comment.
Herald added subscribers: srhines, danalbert, tberghammer.
Updated diff as per suggestion.
Repository:
rL LLVM
http://reviews.llvm.org/D18082
Files:
source/Plugins/Platform/Android/PlatformAndroidRemoteGDBServer.
nitesh.jain added a comment.
Hi Tamas Berghammer,
Is it ok to commit?
Repository:
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http://reviews.llvm.org/D18082
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nitesh.jain created this revision.
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nitesh.jain added subscribers: jaydeep, bhushan, sagar, mohit.bhakkad,
lldb-commits.
These patch will set clang::TargetOptions::ABI and accordingly code will be
generated For MIPS target.
http://reviews.llvm.org/
nitesh.jain set the repository for this revision to rL LLVM.
nitesh.jain updated this revision to Diff 52177.
nitesh.jain added a comment.
Corrected formatting issue
Repository:
rL LLVM
http://reviews.llvm.org/D18638
Files:
include/lldb/Core/ArchSpec.h
source/Core/ArchSpec.cpp
source/P
nitesh.jain added a comment.
Yes this function is clang specific(even GetClangTargetCPU) .Will update the
diff as per suggestion.
Thanks
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nitesh.jain updated this revision to Diff 52886.
nitesh.jain added a comment.
The diff is updated as per suggestion
Repository:
rL LLVM
http://reviews.llvm.org/D18638
Files:
source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
source/Plugins/ExpressionParser/Clang/ClangExpress
nitesh.jain created this revision.
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Herald added a subscriber: sdardis.
Currently floating point regsiters has "eE
nitesh.jain created this revision.
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The ArchSpec::m_flags will be set based on ELF flag ABI.
Repository
nitesh.jain added inline comments.
Comment at: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp:1625-1626
@@ -1624,4 +1624,4 @@
if (arch_spec.GetMachine() == llvm::Triple::mips ||
arch_spec.GetMachine() == llvm::Triple::mipsel
|| arch_spec.G
nitesh.jain created this revision.
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nitesh.jain set the repository for this revision to rL LLVM.
Repository:
rL LLVM
http://reviews.llvm.org/D12671
Files:
sour
nitesh.jain updated the summary for this revision.
nitesh.jain updated this revision to Diff 34146.
nitesh.jain added a comment.
Added include/lldb/Core/ArchSpec.h diff
Repository:
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http://reviews.llvm.org/D12671
Files:
include/lldb/Core/ArchSpec.h
source/Core/ArchSpec.cpp
sourc
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