https://github.com/mariusz-sikora-at-amd updated
https://github.com/llvm/llvm-project/pull/74576
>From 23759746b66c33028ad2340b1e98067ebf1f8074 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 28 Jun 2022 15:24:24 -0700
Subject: [PATCH] [AMDGPU] GFX12: select @llvm.prefetch intri
@@ -959,6 +967,32 @@ def : GCNPat <
}
} // let OtherPredicates = [HasShaderCyclesRegister]
+def SIMM24bitPtr : ImmLeaf (Imm);}]
+>;
+
+multiclass SMPrefetchPat {
+ def : GCNPat <
+(smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32
cache_type)),
+(!cas
https://github.com/mariusz-sikora-at-amd updated
https://github.com/llvm/llvm-project/pull/74576
>From 23759746b66c33028ad2340b1e98067ebf1f8074 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 28 Jun 2022 15:24:24 -0700
Subject: [PATCH 1/2] [AMDGPU] GFX12: select @llvm.prefetch i
https://github.com/mariusz-sikora-at-amd closed
https://github.com/llvm/llvm-project/pull/74836
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
@@ -684,6 +684,51 @@ s_rndne_f16 s5, 0xfe0b
s_rndne_f16 s5, 0x3456
// GFX12: encoding: [0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00]
+s_barrier_signal -2
mariusz-sikora-at-amd wrote:
Thanks !
https://github.com/llvm/llvm-project/pull/74836
__
@@ -684,6 +684,51 @@ s_rndne_f16 s5, 0xfe0b
s_rndne_f16 s5, 0x3456
// GFX12: encoding: [0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00]
+s_barrier_signal -2
mariusz-sikora-at-amd wrote:
Patch: https://github.com/llvm/llvm-project/pull/75575
https://github.com/llvm/
https://github.com/mariusz-sikora-at-amd updated
https://github.com/llvm/llvm-project/pull/74576
>From 23759746b66c33028ad2340b1e98067ebf1f8074 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 28 Jun 2022 15:24:24 -0700
Subject: [PATCH 1/4] [AMDGPU] GFX12: select @llvm.prefetch i
https://github.com/mariusz-sikora-at-amd closed
https://github.com/llvm/llvm-project/pull/74576
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
https://github.com/mariusz-sikora-at-amd updated
https://github.com/llvm/llvm-project/pull/75625
>From de5303eb8a9e061dbd365922f85cad02bca5ec26 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 5 Jul 2022 11:41:29 -0700
Subject: [PATCH 1/3] GFX12: Add LoopDataPrefetchPass
It is c
https://github.com/mariusz-sikora-at-amd updated
https://github.com/llvm/llvm-project/pull/75625
>From de5303eb8a9e061dbd365922f85cad02bca5ec26 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 5 Jul 2022 11:41:29 -0700
Subject: [PATCH 1/4] GFX12: Add LoopDataPrefetchPass
It is c
https://github.com/mariusz-sikora-at-amd closed
https://github.com/llvm/llvm-project/pull/75625
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
https://github.com/mariusz-sikora-at-amd updated
https://github.com/llvm/llvm-project/pull/77892
>From 628a3d2b42cdcbd903e0830ab7d631ea7dc422b9 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 10 Jan 2024 12:17:58 +0100
Subject: [PATCH 1/2] AMDGPU/GFX12: Add new dot4 fp8/bf8 instructio
mariusz-sikora-at-amd wrote:
Rebase to run tests
https://github.com/llvm/llvm-project/pull/77892
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
https://github.com/mariusz-sikora-at-amd closed
https://github.com/llvm/llvm-project/pull/77892
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
mariusz-sikora-at-amd wrote:
> Can you add a GFX12 RUN line to
> clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl? That will probably require
> adding "fp8-conversion-insts" to the GFX12 part of TargetParser.cpp. You can
> do this in a separate patch if you want.
Done
https://github.com/llvm/
mariusz-sikora-at-amd wrote:
> Why is so there so much special casing in the assembler/disassembler?
I'm not an original author of these change, but from what I understand it is a
workaround to handle VOP3 instructions which have a single source but require
the use of two bits from OPSEL.
`V_C
@@ -626,11 +629,82 @@ class Cvt_PK_F32_F8_Pat;
-foreach Index = [0, -1] in {
- def : Cvt_PK_F32_F8_Pat;
- def : Cvt_PK_F32_F8_Pat;
+let SubtargetPredicate = isGFX9Only in {
+ foreach Index = [0, -1] in {
+def : Cvt_PK_F32_F8_Pat;
+def : Cvt_PK_F32_F8_Pat;
+ }
+}
+
+
https://github.com/mariusz-sikora-at-amd edited
https://github.com/llvm/llvm-project/pull/78414
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
mariusz-sikora-at-amd wrote:
> > Correct, some of these instructions use opsel[1] which in LLVM in stored in
> > src1_modifiers so a dummy src1 is used.
>
> Why can't we just use `SRCMODS.OP_SEL_1` with src0?
When referring to `SRCMODS.OP_SEL_1` you are referring to `src1_modifier`
(second bi
Mirko =?utf-8?q?Brkušanin?= ,
Mirko =?utf-8?q?Brkušanin?= ,Mirko Brkusanin
,Mariusz Sikora
Message-ID:
In-Reply-To:
@@ -8770,6 +8781,22 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const
OperandVector &Operands,
}
}
+int VdstInIdx = AMDGPU::getNamedOper
Mirko =?utf-8?q?Brkušanin?= ,
Mirko =?utf-8?q?Brkušanin?= ,Mirko Brkusanin
,Mariusz Sikora
Message-ID:
In-Reply-To:
https://github.com/mariusz-sikora-at-amd closed
https://github.com/llvm/llvm-project/pull/78414
___
lldb-commits mailing list
lldb-co
21 matches
Mail list logo
