[Lldb-commits] [mlir] [llvm] [libc] [clang] [libcxx] [lldb] [clang-tools-extra] [compiler-rt] [flang] intrinsic to generate a bfi instruction (PR #79672)

https://github.com/inclyc edited https://github.com/llvm/llvm-project/pull/79672 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [libc] [libcxx] [lldb] [clang] [compiler-rt] [clang-tools-extra] [mlir] [flang] [llvm] intrinsic to generate a bfi instruction (PR #79672)

https://github.com/inclyc commented: Also I kindly wonder if this intrinsic is necessary for optimization/codegen. Why not prefer inline assembly? https://github.com/llvm/llvm-project/pull/79672 ___ lldb-commits mailing list lldb-commits@lists.llvm.or

[Lldb-commits] [compiler-rt] [clang] [llvm] [mlir] [flang] [libc] [lldb] [clang-tools-extra] [libcxx] intrinsic to generate a bfi instruction (PR #79672)

@@ -2558,6 +2558,14 @@ def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)), def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)), (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>; +def SDT_AArch64BFI_32bit : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, +

[Lldb-commits] [compiler-rt] [clang] [llvm] [mlir] [flang] [libc] [lldb] [clang-tools-extra] [libcxx] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

https://github.com/inclyc edited https://github.com/llvm/llvm-project/pull/79672 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [libc] [clang-tools-extra] [lldb] [flang] [mlir] [llvm] [clang] [compiler-rt] [libcxx] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

davemgreen wrote: Hello. Can you explain why this is needed, as opposed to using the equivalent shift/and/ors? https://github.com/llvm/llvm-project/pull/79672 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mai

[Lldb-commits] [libcxx] [lld] [clang] [libc] [compiler-rt] [flang] [lldb] [clang-tools-extra] [llvm] [VPlan] Implement cloning of VPlans. (PR #73158)

Enna1 wrote: Hi @fhahn I think this change introduce a memory leak in `VPlan::duplicate()`, see https://lab.llvm.org/buildbot/#/builders/168/builds/18308/steps/10/logs/stdio Can you take a look? https://github.com/llvm/llvm-project/pull/73158 ___ ll

[Lldb-commits] [lldb] [clang] [llvm] [clang-tools-extra] [compiler-rt] [mlir] [libc] [flang] [OpenMP] atomic compare weak : Parser & AST support (PR #79475)

https://github.com/SunilKuravinakop updated https://github.com/llvm/llvm-project/pull/79475 >From 6614e517cf0888b4502efc0af974d1612fa7a822 Mon Sep 17 00:00:00 2001 From: Sunil Kuravinakop Date: Thu, 25 Jan 2024 10:37:20 -0600 Subject: [PATCH 1/2] Changes to Support Parsing & Sema of atomic comp

[Lldb-commits] [libcxx] [flang] [libc] [clang-tools-extra] [clang] [llvm] [compiler-rt] [libunwind] [lld] [lldb] [X86] Use RORX over SHR imm (PR #77964)

@@ -4216,6 +4217,95 @@ MachineSDNode *X86DAGToDAGISel::emitPCMPESTR(unsigned ROpc, unsigned MOpc, return CNode; } +// When the consumer of a right shift (arithmetic or logical) wouldn't notice +// the difference if the instruction was a rotate right instead (because the +//

[Lldb-commits] [flang] [compiler-rt] [clang-tools-extra] [clang] [llvm] [libc] [lldb] [mlir] [libcxx] [AArch64] add intrinsic to generate a bfi instruction (PR #79672)

RamaMalladiAWS wrote: > Hello. Can you explain why this is needed, as opposed to using the equivalent > shift/and/ors? Hi @davemgreen, one of AWS customers requested for such an intrinsic to be made available so that they could consume it their IR directly. The reasoning they had was to use 1

[Lldb-commits] [libc] [clang-tools-extra] [mlir] [lldb] [flang] [compiler-rt] [libcxx] [llvm] [libunwind] [clang] [lld] Reland: [libc++][format] P2637R3: Member visit (std::basic_format_arg) #76449 (P

mordante wrote: > @mordante I guess the PR missed LLVM18 release. I'll update the release notes > accordingly. Is that OK? Yes. It would have been nice to get this in LLVM 18, but I don't feel it's critical to backport it. (Especially since it's a C++26 only feature and I expect very few peop

[Lldb-commits] [libc] [clang-tools-extra] [lldb] [flang] [compiler-rt] [libcxx] [llvm] [libunwind] [clang] [lld] [X86] Use RORX over SHR imm (PR #77964)

https://github.com/Bryce-MW updated https://github.com/llvm/llvm-project/pull/77964 >From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001 From: Bryce Wilson Date: Fri, 12 Jan 2024 16:01:32 -0600 Subject: [PATCH 01/16] [X86] Use RORX over SHR imm --- llvm/lib/Target/X86/X86In

[Lldb-commits] [libc] [clang-tools-extra] [lldb] [flang] [compiler-rt] [libcxx] [llvm] [libunwind] [clang] [lld] [X86] Use RORX over SHR imm (PR #77964)

https://github.com/Bryce-MW updated https://github.com/llvm/llvm-project/pull/77964 >From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001 From: Bryce Wilson Date: Fri, 12 Jan 2024 16:01:32 -0600 Subject: [PATCH 01/16] [X86] Use RORX over SHR imm --- llvm/lib/Target/X86/X86In

[Lldb-commits] [llvm] [libcxx] [lldb] [compiler-rt] [flang] [libc] [clang] [lld] [clang-tools-extra] [VPlan] Implement cloning of VPlans. (PR #73158)

fhahn wrote: @Enna1 thanks, should be fixed by 1b37e8087e1e1ecf5aadd8da536ee17dc21832e2. Bot should be back to green https://github.com/llvm/llvm-project/pull/73158 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-b

[Lldb-commits] [flang] [mlir] [lldb] [libcxxabi] [llvm] [clang-tools-extra] [libcxx] [libc] [clang] [lld] [compiler-rt] [mlir][complex] Prevent underflow in complex.abs (PR #76316)

Lewuathe wrote: @joker-eph Oh, sorry for bothering you. I'll check what's going on. https://github.com/llvm/llvm-project/pull/76316 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb] Implement WebAssembly debugging (PR #77949)

xujuntwt95329 wrote: > > Hi @mh4ck-Thales this is caused by [#77949 > > (comment)](https://github.com/llvm/llvm-project/pull/77949#discussion_r1463458728), > > currently we need to modify it manually. > > Thanks! That did the trick for the breakpoint and disassembly problems. When > using `re