https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/78970
>From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 22 Jan 2024 21:11:42 +0800
Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/78970
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Fznamznon wrote:
> So I guess we should set the DefaultedDestructorIsConstexpr to false and only
> use it for warning?
I'm not sure? Switching all constexpr-related errors to warnings doesn't seem
right, even though almost all functions now can be marked constexpr, they still
can't be called
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/78113
>From 36b085f21b76d7bf7c9965a86a09d1cef4fe9329 Mon Sep 17 00:00:00 2001
From: Florian Hahn
Date: Sun, 14 Jan 2024 14:13:08 +
Subject: [PATCH 1/5] [VPlan] Add new VPUniformPerUFRecipe, use for step
truncation.
cor3ntin wrote:
> So I guess we should set the DefaultedDestructorIsConstexpr to false and only
> use it for warning?
Oh gosh, I'm an idiot, i meant **`true`**
https://github.com/llvm/llvm-project/pull/77753
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https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/78113
>From 36b085f21b76d7bf7c9965a86a09d1cef4fe9329 Mon Sep 17 00:00:00 2001
From: Florian Hahn
Date: Sun, 14 Jan 2024 14:13:08 +
Subject: [PATCH 1/6] [VPlan] Add new VPUniformPerUFRecipe, use for step
truncation.
@@ -1469,6 +1461,52 @@ void VPReplicateRecipe::print(raw_ostream &O, const
Twine &Indent,
}
#endif
+static bool isUniformAcrossVFsAndUFs(VPScalarCastRecipe *C) {
fhahn wrote:
Added comment + TODO, thanks!
https://github.com/llvm/llvm-project/pull/78113
@@ -230,7 +230,11 @@ Type *VPTypeAnalysis::inferScalarType(const VPValue *V) {
return V->getUnderlyingValue()->getType();
})
.Case(
- [](const VPWidenCastRecipe *R) { return R->getResultType(); });
+ [](const VPWidenCast
https://github.com/fhahn edited https://github.com/llvm/llvm-project/pull/78113
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https://github.com/fhahn commented:
Comments should be addressed and title & description updated, thanks!
https://github.com/llvm/llvm-project/pull/78113
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@@ -1469,6 +1461,52 @@ void VPReplicateRecipe::print(raw_ostream &O, const
Twine &Indent,
}
#endif
+static bool isUniformAcrossVFsAndUFs(VPScalarCastRecipe *C) {
+ return C->isDefinedOutsideVectorRegions() ||
+ isa(C->getOperand(0)) ||
+ isa(C->getOperand(0))
@@ -498,10 +498,34 @@ static VPValue *createScalarIVSteps(VPlan &Plan, const
InductionDescriptor &ID,
VPCanonicalIVPHIRecipe *CanonicalIV = Plan.getCanonicalIV();
Type *TruncTy = TruncI ? TruncI->getType() : IVTy;
VPValue *BaseIV = CanonicalIV;
fhahn wro
https://github.com/H-G-Hristov updated
https://github.com/llvm/llvm-project/pull/79032
>From e03452fda84a5284420bba1913299b68caabb6cd Mon Sep 17 00:00:00 2001
From: Zingam
Date: Mon, 22 Jan 2024 20:35:00 +0200
Subject: [PATCH 1/2] Revert "Revert "[libc++][format] P2637R3: Member `visit`
(`std:
mh4ck-Thales wrote:
I already tried to use `register read` to access Wasm variables without
success. But it was the patch available
[here](https://github.com/bytecodealliance/wasm-micro-runtime/blob/main/build-scripts/lldb_wasm.patch)
is part of WAMR, maybe this patch is different and will mak
xujuntwt95329 wrote:
> I already tried to use `register read` to access Wasm variables without
> success. But it was the patch available
> [here](https://github.com/bytecodealliance/wasm-micro-runtime/blob/main/build-scripts/lldb_wasm.patch)
> is part of WAMR, maybe this patch is different and
@@ -4216,6 +4217,97 @@ MachineSDNode *X86DAGToDAGISel::emitPCMPESTR(unsigned
ROpc, unsigned MOpc,
return CNode;
}
+// When the consumer of a right shift (arithmetic or logical) wouldn't notice
+// the difference if the instruction was a rotate right instead (because the
+//
https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/77964
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@@ -4216,6 +4217,97 @@ MachineSDNode *X86DAGToDAGISel::emitPCMPESTR(unsigned
ROpc, unsigned MOpc,
return CNode;
}
+// When the consumer of a right shift (arithmetic or logical) wouldn't notice
+// the difference if the instruction was a rotate right instead (because the
+//
https://github.com/RKSimon requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/77964
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@@ -4216,6 +4217,97 @@ MachineSDNode *X86DAGToDAGISel::emitPCMPESTR(unsigned
ROpc, unsigned MOpc,
return CNode;
}
+// When the consumer of a right shift (arithmetic or logical) wouldn't notice
+// the difference if the instruction was a rotate right instead (because the
+//
Author: Alexandre Ganea
Date: 2024-01-25T09:34:18-05:00
New Revision: 03e4070ce1f834eb426aa8f8622838c40ff5c710
URL:
https://github.com/llvm/llvm-project/commit/03e4070ce1f834eb426aa8f8622838c40ff5c710
DIFF:
https://github.com/llvm/llvm-project/commit/03e4070ce1f834eb426aa8f8622838c40ff5c710.dif
@@ -614,6 +614,61 @@ void VPBasicBlock::print(raw_ostream &O, const Twine
&Indent,
printSuccessors(O, Indent);
}
#endif
+static void cloneCFG(VPBlockBase *Entry,
+ DenseMap &Old2NewVPBlocks);
+
+static VPBlockBase *cloneVPB(VPBlockBase *BB) {
@@ -614,6 +614,61 @@ void VPBasicBlock::print(raw_ostream &O, const Twine
&Indent,
printSuccessors(O, Indent);
}
#endif
+static void cloneCFG(VPBlockBase *Entry,
+ DenseMap &Old2NewVPBlocks);
ayalz wrote:
This cloning is recursive, so pe
@@ -1594,6 +1657,13 @@ class VPWidenPHIRecipe : public VPHeaderPHIRecipe {
addOperand(Start);
}
+ VPRecipeBase *clone() override {
+auto *Res = new VPWidenPHIRecipe(cast(getUnderlyingInstr()),
ayalz wrote:
Better mark it unreachable than have unt
@@ -982,6 +1037,94 @@ void VPlan::updateDominatorTree(DominatorTree *DT,
BasicBlock *LoopHeaderBB,
assert(DT->verify(DominatorTree::VerificationLevel::Fast));
}
+static void remapOperands(VPBlockBase *Entry, VPBlockBase *NewEntry,
+ DenseMap &Old2Ne
@@ -982,6 +1037,94 @@ void VPlan::updateDominatorTree(DominatorTree *DT,
BasicBlock *LoopHeaderBB,
assert(DT->verify(DominatorTree::VerificationLevel::Fast));
}
+static void remapOperands(VPBlockBase *Entry, VPBlockBase *NewEntry,
+ DenseMap &Old2Ne
@@ -614,6 +614,61 @@ void VPBasicBlock::print(raw_ostream &O, const Twine
&Indent,
printSuccessors(O, Indent);
}
#endif
+static void cloneCFG(VPBlockBase *Entry,
+ DenseMap &Old2NewVPBlocks);
+
+static VPBlockBase *cloneVPB(VPBlockBase *BB) {
+ if (auto
@@ -614,6 +614,61 @@ void VPBasicBlock::print(raw_ostream &O, const Twine
&Indent,
printSuccessors(O, Indent);
}
#endif
+static void cloneCFG(VPBlockBase *Entry,
+ DenseMap &Old2NewVPBlocks);
+
+static VPBlockBase *cloneVPB(VPBlockBase *BB) {
+ if (auto
@@ -982,6 +1037,94 @@ void VPlan::updateDominatorTree(DominatorTree *DT,
BasicBlock *LoopHeaderBB,
assert(DT->verify(DominatorTree::VerificationLevel::Fast));
}
+static void remapOperands(VPBlockBase *Entry, VPBlockBase *NewEntry,
+ DenseMap &Old2Ne
@@ -982,6 +1037,94 @@ void VPlan::updateDominatorTree(DominatorTree *DT,
BasicBlock *LoopHeaderBB,
assert(DT->verify(DominatorTree::VerificationLevel::Fast));
}
+static void remapOperands(VPBlockBase *Entry, VPBlockBase *NewEntry,
+ DenseMap &Old2Ne
@@ -2694,6 +2852,9 @@ class VPlan {
/// been modeled in VPlan directly.
DenseMap SCEVToExpansion;
+ /// Construct an uninitialized VPlan, should be used for cloning only.
+ explicit VPlan() = default;
+
ayalz wrote:
Is it really needed? (See above)
htt
mh4ck-Thales wrote:
> Hi @mh4ck-Thales this is caused by [#77949
> (comment)](https://github.com/llvm/llvm-project/pull/77949#discussion_r1463458728),
> currently we need to modify it manually.
Thanks! That did the trick for the breakpoint and disassembly problems. When
using `read register`
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/15] [X86] Use RORX over SHR imm
---
llvm/lib/Target/X86/X86In
@@ -4216,6 +4217,97 @@ MachineSDNode *X86DAGToDAGISel::emitPCMPESTR(unsigned
ROpc, unsigned MOpc,
return CNode;
}
+// When the consumer of a right shift (arithmetic or logical) wouldn't notice
+// the difference if the instruction was a rotate right instead (because the
+//
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
@@ -1469,6 +1461,52 @@ void VPReplicateRecipe::print(raw_ostream &O, const
Twine &Indent,
}
#endif
+static bool isUniformAcrossVFsAndUFs(VPScalarCastRecipe *C) {
+ return C->isDefinedOutsideVectorRegions() ||
+ isa(C->getOperand(0)) ||
+ isa(C->getOperand(0))
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
https://github.com/ayalz edited https://github.com/llvm/llvm-project/pull/78113
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@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
https://github.com/ayalz commented:
Looks good to me, adding some minor suggestions.
https://github.com/llvm/llvm-project/pull/78113
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@@ -859,6 +859,7 @@ class VPSingleDefRecipe : public VPRecipeBase, public
VPValue {
case VPRecipeBase::VPWidenIntOrFpInductionSC:
case VPRecipeBase::VPWidenPointerInductionSC:
case VPRecipeBase::VPReductionPHISC:
+case VPRecipeBase::VPScalarCastSC:
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
@@ -513,29 +547,125 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->
@@ -513,29 +547,125 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->
https://github.com/felipepiovezan approved this pull request.
https://github.com/llvm/llvm-project/pull/79215
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@@ -513,29 +547,125 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/78113
>From 36b085f21b76d7bf7c9965a86a09d1cef4fe9329 Mon Sep 17 00:00:00 2001
From: Florian Hahn
Date: Sun, 14 Jan 2024 14:13:08 +
Subject: [PATCH 1/7] [VPlan] Add new VPUniformPerUFRecipe, use for step
truncation.
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
https://github.com/fhahn commented:
Address latest comments, thanks!
https://github.com/llvm/llvm-project/pull/78113
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@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
https://github.com/fhahn edited https://github.com/llvm/llvm-project/pull/78113
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@@ -859,6 +859,7 @@ class VPSingleDefRecipe : public VPRecipeBase, public
VPValue {
case VPRecipeBase::VPWidenIntOrFpInductionSC:
case VPRecipeBase::VPWidenPointerInductionSC:
case VPRecipeBase::VPReductionPHISC:
+case VPRecipeBase::VPScalarCastSC:
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
@@ -1469,6 +1461,52 @@ void VPReplicateRecipe::print(raw_ostream &O, const
Twine &Indent,
}
#endif
+static bool isUniformAcrossVFsAndUFs(VPScalarCastRecipe *C) {
+ return C->isDefinedOutsideVectorRegions() ||
+ isa(C->getOperand(0)) ||
+ isa(C->getOperand(0))
@@ -491,19 +491,41 @@ void VPlanTransforms::removeDeadRecipes(VPlan &Plan) {
static VPValue *createScalarIVSteps(VPlan &Plan, const InductionDescriptor &ID,
ScalarEvolution &SE, Instruction *TruncI,
-Type
jimingham wrote:
LGTM
https://github.com/llvm/llvm-project/pull/79215
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https://github.com/justinfargnoli edited
https://github.com/llvm/llvm-project/pull/67866
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Author: Kazu Hirata
Date: 2024-01-25T10:39:24-08:00
New Revision: 89dc7063f6c81d468a61b71b4ca612e22cb87a46
URL:
https://github.com/llvm/llvm-project/commit/89dc7063f6c81d468a61b71b4ca612e22cb87a46
DIFF:
https://github.com/llvm/llvm-project/commit/89dc7063f6c81d468a61b71b4ca612e22cb87a46.diff
L
https://github.com/MaskRay edited
https://github.com/llvm/llvm-project/pull/79239
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https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF
https://github.com/jhuber6 updated
https://github.com/llvm/llvm-project/pull/79373
>From 145b7bc932ce3ffa46545cd7af29b1c93981429c Mon Sep 17 00:00:00 2001
From: Joseph Huber
Date: Wed, 24 Jan 2024 15:34:00 -0600
Subject: [PATCH 1/3] [NVPTX] Add support for -march=native in standalone NVPTX
Sum
jhuber6 wrote:
> On the other hand, I'd be OK with providing --offload-arch=native translating
> into "compile for all present GPU variants", with a possibility to further
> adjust the selected set with the usual --no-offload-arch-foo, if the user
> needs to. This will at least produce code th
Author: Alex Langford
Date: 2024-01-25T11:14:53-08:00
New Revision: 59a6525a4b9d46b931021f727b3235415bc82ea5
URL:
https://github.com/llvm/llvm-project/commit/59a6525a4b9d46b931021f727b3235415bc82ea5
DIFF:
https://github.com/llvm/llvm-project/commit/59a6525a4b9d46b931021f727b3235415bc82ea5.diff
https://github.com/bulbazord closed
https://github.com/llvm/llvm-project/pull/79215
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@@ -513,29 +547,125 @@ void RISCV::relocate(uint8_t *loc, const Relocation
&rel, uint64_t val) const {
break;
case R_RISCV_RELAX:
-return; // Ignored (for now)
-
+return;
+ case R_RISCV_TLSDESC:
+// The addend is stored in the second word.
+if (config->
https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79239
>From 3725fa4eac3d3d946289d7eb7213f3a1751a2770 Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 17:58:07 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF
Artem-B wrote:
> This is what we already do for `--offload-arch=native` on CUDA, but this is
> somewhat tangential. I've updated this patch to present the warning in the
> case of multiply GPUs being detected, so I don't think there's a concern here
> with the user being confused. If they have
jhuber6 wrote:
> User confusion is only part of the issue here. With any single GPU choice we
> would still potentially produce a nonworking binary, if our GPU choice does
> not match what the user wants.
>
> "all GPUs" has the advantage of always producing the binary that's guaranteed
> to wo
https://github.com/ilovepi approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/79256
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pirama-arumuga-nainar wrote:
@llvm/clang-vendors Adding clang vendors. FYI, this change expands error
reporting on invalid version numbers to all target triples (This was previously
restricted to Android triples). This can have potential downstream impact.
Please review/test and let us know
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/15] [X86] Use RORX over SHR imm
---
llvm/lib/Target/X86/X86In
Bryce-MW wrote:
I think the fail on Windows is not related. Hopefully a merge fixes it...
https://github.com/llvm/llvm-project/pull/77964
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https://github.com/MaskRay updated
https://github.com/llvm/llvm-project/pull/79256
>From be08e64c2c1f433b017185ce78525ad097e609be Mon Sep 17 00:00:00 2001
From: Fangrui Song
Date: Tue, 23 Jan 2024 21:37:04 -0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF
Artem-B wrote:
> I think the semantics of native on other architectures are clear enough here.
I don't think we have the same idea about that. Let's spell it out, so there's
no confusion.
[GCC
manual](https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html#index-march-16)
says:
> Using -march=na
@@ -1443,15 +1443,17 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) {
const ToolChain &TC = getToolChain(
*UArgs, computeTargetTriple(*this, TargetTriple, *UArgs));
- if (TC.getTriple().isAndroid()) {
-llvm::Triple Triple = TC.getTriple();
-StringR
https://github.com/MaskRay edited
https://github.com/llvm/llvm-project/pull/78655
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@@ -255,7 +255,7 @@ class Triple {
Cygnus,
CoreCLR,
Simulator, // Simulator variants of other systems, e.g., Apple's iOS
-MacABI, // Mac Catalyst variant of Apple's iOS deployment target.
+MacABI,// Mac Catalyst variant of Apple's iOS deployment target.
@@ -276,7 +276,7 @@ class Triple {
Callable,
Mesh,
Amplification,
-
+OpenCL,
MaskRay wrote:
I wonder why we need this addition. This is not mentioned in the description.
https://github.com/llvm/llvm-project/pull/78655
_
jhuber6 wrote:
> > I think the semantics of native on other architectures are clear enough
> > here.
>
> I don't think we have the same idea about that. Let's spell it out, so
> there's no confusion.
>
> [GCC
> manual](https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html#index-march-16)
> sa
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/73158
>From 13a26e8e7440c3b501730b22588af393a3e543cd Mon Sep 17 00:00:00 2001
From: Florian Hahn
Date: Thu, 6 Jul 2023 08:07:45 +0100
Subject: [PATCH 1/3] [VPlan] Implement cloning of VPlans.
This patch implements clonin
Artem-B wrote:
> This method of compilation is not like CUDA, so we can't target all the GPUs
> at the same time.
I think this is the key fact I was missing. If the patch is only for a
standalone compilation which does not do multi-GPU compilation in principle,
then your approach makes sense.
@@ -276,7 +276,7 @@ class Triple {
Callable,
Mesh,
Amplification,
-
+OpenCL,
ZijunZhaoCCK wrote:
Some cases like
https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGenOpenCL/amdgpu-alignment.cl#L3
https://github.com/llvm/llvm-proje
jhuber6 wrote:
> > This method of compilation is not like CUDA, so we can't target all the
> > GPUs at the same time.
>
> I think this is the key fact I was missing. If the patch is only for a
> standalone compilation which does not do multi-GPU compilation in principle,
> then your approach
https://github.com/jkorous-apple updated
https://github.com/llvm/llvm-project/pull/79392
>From dcc2b0c07681b57dbd5a82ce83f5166bb3b9ee09 Mon Sep 17 00:00:00 2001
From: Jan Korous
Date: Wed, 24 Jan 2024 15:02:55 -0800
Subject: [PATCH] [-Wunsafe-buffer-usage] Fix AST matcher of UUCAddAssignGadget
@@ -2694,6 +2852,9 @@ class VPlan {
/// been modeled in VPlan directly.
DenseMap SCEVToExpansion;
+ /// Construct an uninitialized VPlan, should be used for cloning only.
+ explicit VPlan() = default;
+
fhahn wrote:
Removed, thanks!
https://github.com/
@@ -614,6 +614,61 @@ void VPBasicBlock::print(raw_ostream &O, const Twine
&Indent,
printSuccessors(O, Indent);
}
#endif
+static void cloneCFG(VPBlockBase *Entry,
+ DenseMap &Old2NewVPBlocks);
fhahn wrote:
Updated as suggested and renamed
@@ -982,6 +1037,94 @@ void VPlan::updateDominatorTree(DominatorTree *DT,
BasicBlock *LoopHeaderBB,
assert(DT->verify(DominatorTree::VerificationLevel::Fast));
}
+static void remapOperands(VPBlockBase *Entry, VPBlockBase *NewEntry,
+ DenseMap &Old2Ne
@@ -1594,6 +1657,13 @@ class VPWidenPHIRecipe : public VPHeaderPHIRecipe {
addOperand(Start);
}
+ VPRecipeBase *clone() override {
+auto *Res = new VPWidenPHIRecipe(cast(getUnderlyingInstr()),
fhahn wrote:
Changed to `llvm_unreachable`, thanks!
@@ -982,6 +1037,94 @@ void VPlan::updateDominatorTree(DominatorTree *DT,
BasicBlock *LoopHeaderBB,
assert(DT->verify(DominatorTree::VerificationLevel::Fast));
}
+static void remapOperands(VPBlockBase *Entry, VPBlockBase *NewEntry,
+ DenseMap &Old2Ne
@@ -982,6 +1037,94 @@ void VPlan::updateDominatorTree(DominatorTree *DT,
BasicBlock *LoopHeaderBB,
assert(DT->verify(DominatorTree::VerificationLevel::Fast));
}
+static void remapOperands(VPBlockBase *Entry, VPBlockBase *NewEntry,
+ DenseMap &Old2Ne
@@ -614,6 +614,61 @@ void VPBasicBlock::print(raw_ostream &O, const Twine
&Indent,
printSuccessors(O, Indent);
}
#endif
+static void cloneCFG(VPBlockBase *Entry,
+ DenseMap &Old2NewVPBlocks);
+
+static VPBlockBase *cloneVPB(VPBlockBase *BB) {
+ if (auto
@@ -614,6 +614,61 @@ void VPBasicBlock::print(raw_ostream &O, const Twine
&Indent,
printSuccessors(O, Indent);
}
#endif
+static void cloneCFG(VPBlockBase *Entry,
+ DenseMap &Old2NewVPBlocks);
+
+static VPBlockBase *cloneVPB(VPBlockBase *BB) {
+ if (auto
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