tgs-sc wrote:
One of them is ASSERT_NE and the other is ASSERT_EQ
https://github.com/llvm/llvm-project/pull/154123
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tgs-sc wrote:
@DavidSpickett, Hi!
I am sorry to bother you third time in this week, but can you please also merge
this PR as I don't have commit access?
@Michael137 approved it, and we were waiting when this one
(https://github.com/llvm/llvm-project/pull/157674) would be merged. I thought
that
tgs-sc wrote:
Oh, I am sorry, but it is not merged as I checked. @Michael137, can you merge
it please?
https://github.com/llvm/llvm-project/pull/154123
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https://github.com/tgs-sc reopened
https://github.com/llvm/llvm-project/pull/154123
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tgs-sc wrote:
> Maybe something should be skipping forward to try and re-sync.
I think that, in general, a situation is always possible in which it is unclear
how to decode the instruction length, so it is hard to imagine how this can be
improved. Now, there are two phases: decode and disassem
tgs-sc wrote:
@DavidSpickett, @JDevlieghere, I think that this patch can be merged.
https://github.com/llvm/llvm-project/pull/164413
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@@ -157,7 +157,9 @@ static lldb::offset_t DumpInstructions(const DataExtractor
&DE, Stream *s,
exe_scope->CalculateExecutionContext(exe_ctx);
disassembler_sp->GetInstructionList().Dump(
s, show_address, show_bytes, show_control_flow_kind, &exe_ctx);
@@ -5,5 +5,8 @@ int main(int argc, const char *argv[]) {
double my_double = 1234.5678;
int my_ints[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22};
uint64_t my_uint64s[] = {0, 1, 2, 3, 4, 5, 6, 7};
+ // assume that 0x is invalid instruction in RISC-V and AArch64
+
@@ -41,6 +41,20 @@ def test_memory_read_c_string(self):
" Consider increasing the maximum read length.",
)
+@skipIf(archs=no_match("^(riscv|aarch64).*"))
+def test_riscv_decode_failure(self):
+"""Test the 'memory read' command with instructi
@@ -41,6 +41,20 @@ def test_memory_read_c_string(self):
" Consider increasing the maximum read length.",
)
+@skipIf(archs=no_match("^(riscv|aarch64).*"))
+def test_riscv_decode_failure(self):
tgs-sc wrote:
Addressed
https://github
@@ -41,6 +41,20 @@ def test_memory_read_c_string(self):
" Consider increasing the maximum read length.",
)
+@skipIf(archs=no_match("^(riscv|aarch64).*"))
+def test_riscv_decode_failure(self):
+"""Test the 'memory read' command with instructi
https://github.com/tgs-sc updated
https://github.com/llvm/llvm-project/pull/164413
>From e923a77a146296c441e86a8f9ca87f372058b48a Mon Sep 17 00:00:00 2001
From: Timur Golubovich
Date: Fri, 17 Oct 2025 12:12:29 +
Subject: [PATCH] [lldb] Added a warning in case of instruction decode failure
@@ -0,0 +1,32 @@
+"""
+Test the 'memory read' command when decoding instruction failures.
+"""
tgs-sc wrote:
I checked on riscv, it works (still fails). Enabled this test also for AArch64.
https://github.com/llvm/llvm-project/pull/164413
https://github.com/tgs-sc updated
https://github.com/llvm/llvm-project/pull/164413
>From aab9c5f56e15b65fc2a9c6b27d4dde75b6fe0a5a Mon Sep 17 00:00:00 2001
From: Timur Golubovich
Date: Fri, 17 Oct 2025 12:12:29 +
Subject: [PATCH] [lldb] Added a warning in case of instruction decode failure
https://github.com/tgs-sc updated
https://github.com/llvm/llvm-project/pull/164413
>From 8a8e09540d0031969b7582e10d596430ce10ac8d Mon Sep 17 00:00:00 2001
From: Timur Golubovich
Date: Fri, 17 Oct 2025 12:12:29 +
Subject: [PATCH] [lldb] Added a warning in case of instruction decode failure
@@ -0,0 +1,32 @@
+"""
+Test the 'memory read' command when decoding instruction failures.
+"""
tgs-sc wrote:
Yes, you are right, currently this warning only triggers if target specific
disasm won't change the size of consumed bytes. In RISC-V it happens only if
@@ -0,0 +1,32 @@
+"""
+Test the 'memory read' command when decoding instruction failures.
+"""
tgs-sc wrote:
> I suggest moving this test to a more generic place and only running it on
> risc-v for the time being. I can add an AArch64 encoding to it.
I wil be g
@@ -157,7 +157,9 @@ static lldb::offset_t DumpInstructions(const DataExtractor
&DE, Stream *s,
exe_scope->CalculateExecutionContext(exe_ctx);
disassembler_sp->GetInstructionList().Dump(
s, show_address, show_bytes, show_control_flow_kind, &exe_ctx);
https://github.com/tgs-sc updated
https://github.com/llvm/llvm-project/pull/164413
>From 5b173972d0f85c07283460a4c3e18a5961a3b26c Mon Sep 17 00:00:00 2001
From: Timur Golubovich
Date: Fri, 17 Oct 2025 12:12:29 +
Subject: [PATCH] [lldb] Added a warning in case of instruction decode failure
tgs-sc wrote:
@Michael137, @JDevlieghere, Hi! Can you please look at this patch?
https://github.com/llvm/llvm-project/pull/164413
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https://github.com/tgs-sc created
https://github.com/llvm/llvm-project/pull/164413
While testing baremetal lldb, I came across a situation that if an instruction
could not be disassembled, lldb will print nothing as an output which might be
a bit strange. I added at least printing warning in t
https://github.com/tgs-sc updated
https://github.com/llvm/llvm-project/pull/154123
>From 42a5c3d74a1a191fda53edf329a2e50fb873cb85 Mon Sep 17 00:00:00 2001
From: Timur Golubovich
Date: Mon, 8 Sep 2025 14:43:50 +0300
Subject: [PATCH] [lldb][DWARFASTParserClang] Added a check for the
specializati
tgs-sc wrote:
@Michael137, can you please then merge this patch? Because I don't have
corresponding rights.
https://github.com/llvm/llvm-project/pull/157674
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https://github.com/llvm/llvm-project/pull/157674
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https://github.com/tgs-sc edited
https://github.com/llvm/llvm-project/pull/157674
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https://github.com/tgs-sc edited
https://github.com/llvm/llvm-project/pull/157674
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https://github.com/tgs-sc edited
https://github.com/llvm/llvm-project/pull/157674
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https://github.com/tgs-sc updated
https://github.com/llvm/llvm-project/pull/154123
>From f158ed36c1045b8b996786b7c022fd26680d95ea Mon Sep 17 00:00:00 2001
From: Timur Golubovich
Date: Mon, 8 Sep 2025 14:43:50 +0300
Subject: [PATCH] [lldb][DWARFASTParserClang] Added a check for the
specializati
tgs-sc wrote:
@Michael137, can you please look at this?
https://github.com/llvm/llvm-project/pull/157674
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https://github.com/tgs-sc closed
https://github.com/llvm/llvm-project/pull/154123
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tgs-sc wrote:
I close it as it is actually merged (42a5c3d74a1a19)
https://github.com/llvm/llvm-project/pull/154123
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@@ -1791,6 +1797,7 @@ bool TypeSystemClang::RecordHasFields(const RecordDecl
*record_decl) {
for (base_class = cxx_record_decl->bases_begin(),
base_class_end = cxx_record_decl->bases_end();
base_class != base_class_end; ++base_class) {
+ assert(record
tgs-sc wrote:
@Michael137, can you please rerun CI to this PR? As
https://github.com/llvm/llvm-project/pull/157674 was merged, this one can be
merged too I think.
https://github.com/llvm/llvm-project/pull/154123
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https://github.com/llvm/llvm-project/pull/157674
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https://github.com/tgs-sc edited
https://github.com/llvm/llvm-project/pull/157674
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https://github.com/tgs-sc edited
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@@ -82,7 +82,7 @@ def test(self):
value = self.expect_expr("temp7", result_type="Foo<__fp16, __fp16>")
tgs-sc wrote:
I can make such changes
```
// '_Float16'
FLOATING_TYPE(Float16, HalfTy)
```
->
```
// '_Float16'
FLOATING_TYPE(Float16, Float16Ty)
```
B
https://github.com/tgs-sc updated
https://github.com/llvm/llvm-project/pull/157674
>From 746101620732788c5f975ac96f83ad90213e1252 Mon Sep 17 00:00:00 2001
From: Timur Golubovich
Date: Tue, 9 Sep 2025 13:39:33 +
Subject: [PATCH] [lldb][TypeSystemClang] Added unique builtins types for
__bf16
@@ -82,7 +82,7 @@ def test(self):
value = self.expect_expr("temp7", result_type="Foo<__fp16, __fp16>")
tgs-sc wrote:
There is a mapping in `clang/include/clang/AST/BuiltinTypes.def` that maps
Float16 to HalfTy, so actually it shouldn't be displayed as _
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