https://github.com/SixWeining approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/124059
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https://github.com/SixWeining approved this pull request.
https://github.com/llvm/llvm-project/pull/126204
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https://github.com/SixWeining closed
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https://github.com/SixWeining closed
https://github.com/llvm/llvm-project/pull/126020
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https://github.com/SixWeining approved this pull request.
https://github.com/llvm/llvm-project/pull/126020
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https://github.com/SixWeining commented:
LGTM with a nit.
LLVM uses squash merge. If you'd to keep the 2 commits, please summit 2 PRs.
https://github.com/llvm/llvm-project/pull/126020
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@@ -36,9 +36,30 @@
0xa03 /* LoongArch Advanced SIMD eXtension registers */
#endif
+#ifndef NT_LOONGARCH_HW_BREAK
+#define NT_LOONGARCH_HW_BREAK 0xa05 /* LoongArch hardware breakpoint
registers */
+#endif
+
+#ifndef NT_LOONGARCH_HW_WATCH
+#define NT_LOONGARCH_HW_WATCH 0x
https://github.com/SixWeining edited
https://github.com/llvm/llvm-project/pull/120664
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@@ -27,6 +27,14 @@
// struct iovec definition
#include
+#ifndef NT_LARCH_LSX
SixWeining wrote:
Why not use the `NT_LOONGARCH_LSX` defined in elf.h?
https://github.com/llvm/llvm-project/pull/120664
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https://github.com/SixWeining commented:
Could you add some tests in `lldb/test/Shell/Register/` ?
https://github.com/llvm/llvm-project/pull/120664
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https://github.com/SixWeining approved this pull request.
https://github.com/llvm/llvm-project/pull/120391
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@@ -337,4 +354,471 @@
NativeRegisterContextLinux_loongarch64::GetExpeditedRegisters(
return expedited_reg_nums;
}
+uint32_t
+NativeRegisterContextLinux_loongarch64::NumSupportedHardwareBreakpoints() {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ // Read hardware breakpo
@@ -337,4 +354,471 @@
NativeRegisterContextLinux_loongarch64::GetExpeditedRegisters(
return expedited_reg_nums;
}
+uint32_t
+NativeRegisterContextLinux_loongarch64::NumSupportedHardwareBreakpoints() {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ // Read hardware breakpo
@@ -337,4 +354,471 @@
NativeRegisterContextLinux_loongarch64::GetExpeditedRegisters(
return expedited_reg_nums;
}
+uint32_t
+NativeRegisterContextLinux_loongarch64::NumSupportedHardwareBreakpoints() {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ // Read hardware breakpo
https://github.com/SixWeining approved this pull request.
LGTM and thanks!
https://github.com/llvm/llvm-project/pull/112296
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@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch core file containing GP
https://github.com/SixWeining commented:
Looks good to me once the `code_formatter` CI fail and fcsr format issues are
addressed.
https://github.com/llvm/llvm-project/pull/112296
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SixWeining wrote:
> For RISC-V I have been using #55383 as the tracking issue for overall
> support. If you want to, you could open a similar issue and write out what
> currently works, and I'll link to it from the [main lldb
> page](https://lldb.llvm.org/#platform-support). Not a requirement,
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch64 core file containing
SixWeining wrote:
> I'm not aware of the current status of LoongArch in LLDB
@DavidSpickett General debugging commands can be used on LoongArch with some
known issues to be addressed. Here is a summary #109394.
For this PR, I have checked locally. I can confirm core dump file could be
debugge
@@ -0,0 +1,84 @@
+//===-- RegisterContextPOSIXCore_loongarch64.cpp
--===//
SixWeining wrote:
Generally one line has 80 characters at most.
https://github.com/llvm/llvm-project/pull/112296
_
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch64 core file containing
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch64 core file containing
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch64 core file containing
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch64 core file containing
SixWeining wrote:
Seems we the same `GetRegisterSetCount` misprint issue as #93297.
https://github.com/llvm/llvm-project/pull/112296
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@@ -0,0 +1,62 @@
+//===-- RegisterContextPOSIXCore_loongarch64.h --*- C++
+//-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifie
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SixWeining wrote:
> When using the lldb command 'target create -- core' on the LoongArch64
> architecture, this part of the code is required.
Do you mean `--core` but not `-- core`?
https://github.com/llvm/llvm-project/pull/112296
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@@ -0,0 +1,87 @@
+//===-- RegisterContextPOSIXCore_loongarch64.cpp
+//--===//
SixWeining wrote:
format
https://github.com/llvm/llvm-project/pull/112296
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@@ -0,0 +1,62 @@
+//===-- RegisterContextPOSIXCore_loongarch64.h --*- C++
+//-*-===//
SixWeining wrote:
ditto
https://github.com/llvm/llvm-project/pull/112296
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https://github.com/SixWeining commented:
@wangleiat may take a look.
https://github.com/llvm/llvm-project/pull/112296
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