[Lldb-commits] [clang] [lldb] [llvm] [AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (PR #114293)

@@ -6,10 +6,10 @@ tbx z0.b, z1.b, z2.b // CHECK: error: instruction requires: sve2 or sme // CHECK-NEXT: tbx z0.b, z1.b, z2.b -.arch_extension sve2-aes -.arch_extension nosve2-aes +.arch_extension sve-aes +.arch_extension nosve-aes labrinea wrote: You may fin

[Lldb-commits] [clang] [lldb] [llvm] [AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (PR #114293)

@@ -6,10 +6,10 @@ tbx z0.b, z1.b, z2.b // CHECK: error: instruction requires: sve2 or sme // CHECK-NEXT: tbx z0.b, z1.b, z2.b -.arch_extension sve2-aes -.arch_extension nosve2-aes +.arch_extension sve-aes +.arch_extension nosve-aes labrinea wrote: > all sve2-

[Lldb-commits] [clang] [lldb] [llvm] [AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (PR #114293)

@@ -769,7 +769,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const { .Case("f32mm", FPU & SveMode && HasMatmulFP32) .Case("f64mm", FPU & SveMode && HasMatmulFP64) .Case("sve2", FPU & SveMode && HasSVE2) - .Case("sve2-pmull128", FPU & SveMode

[Lldb-commits] [clang] [lldb] [llvm] Revert "[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114… (PR #115539)

https://github.com/labrinea approved this pull request. https://github.com/llvm/llvm-project/pull/115539 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [clang] [lldb] [llvm] [AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (PR #114293)

https://github.com/labrinea edited https://github.com/llvm/llvm-project/pull/114293 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [clang] [lldb] [llvm] [AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (PR #114293)

@@ -78,7 +78,7 @@ def : FMVExtension<"sme2", "FEAT_SME2", "+sme2,+sme,+bf16", 580>; def : FMVExtension<"ssbs", "FEAT_SSBS2", "+ssbs", 490>; def : FMVExtension<"sve", "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>; def : FMVExtension<"sve2", "FEAT_SVE2", "+sve2,+sve,+fullf

[Lldb-commits] [clang] [lldb] [llvm] [AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (PR #114293)

@@ -365,9 +365,12 @@ def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2", "FEAT_SVE2", "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE, FeatureUseScalarIncVL]>; -def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES", +def FeatureSVEAES : Exte

[Lldb-commits] [clang] [lldb] [llvm] [AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (PR #114293)

@@ -6,10 +6,10 @@ tbx z0.b, z1.b, z2.b // CHECK: error: instruction requires: sve2 or sme // CHECK-NEXT: tbx z0.b, z1.b, z2.b -.arch_extension sve2-aes -.arch_extension nosve2-aes +.arch_extension sve-aes +.arch_extension nosve-aes labrinea wrote: Here you ar

[Lldb-commits] [clang] [lldb] [llvm] [AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (PR #114293)

labrinea wrote: This doesn't seem right. The breaks https://github.com/llvm/llvm-project/pull/113281. I can see your commit https://github.com/llvm/llvm-project/pull/114293/commits/ec6f646e905c16a161487fea34c7dea09635c150 which tries to address it. The patch suggests that the FMV feature sve2-