On Fri, 2017-08-11 at 15:46 +0200, Philipp Zabel wrote:
> Hi Eugeniy,
>
> On Thu, 2017-08-10 at 19:41 +0300, Eugeniy Paltsev wrote:
> > ARC AXS10x boards support custom IP-block which allows to control
> > reset signals of selected peripherals. For example DW GMAC, etc...
> > This block is control
DW ethernet controller on HSDK hangs sometimes after SW reset, so
add reset node to make possible to reset DW ethernet controller HW.
Signed-off-by: Eugeniy Paltsev
---
Changes v1 -> v2:
* Enable HSDK reset driver in hsdk_defconfig
arch/arc/boot/dts/hsdk.dts | 9 +
arch/arc/confi
Print cpu frequency at boot time. In case we have pre-defined
cpu frequency value in device tree try to set it.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/kernel/setup.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/arch/arc/kernel/setup.
We set AXS103 cpu frequency in arch/arc/plat-axs10x/axs10x.c
via direct writing to pll registers for historical reasons.
So get rid of AXS103 platform specific cpu clock configuration as
we have driver for AXS103 core pll (AXS103 pll driver is already
in linux-next. It is selected automatically whe
Set cpu frequency explicitly via "cpu-freq" param in cpu 0 node
in device tree.
We add "cpu-freq" only to cpu 0 as all cpus are clocking from same
clock source (same pll in our case).
We override cpus node in skeleton as we don't need this change for
nsim.
Signed-off-by: Eugeniy Paltsev
---
ar
Use cpu's node "cpu-freq" param instead of platform-specific
"/cpu_card/core_clk" as it works only if we use fixed-clock for cpu
clocking.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/plat-axs10x/axs10x.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/arc/pl
Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/axc003.dtsi | 11 +--
arch/arc/boot/dts/axc003_idu.dtsi | 11
* Set and print cpu frequency at boot time generic way.
* Get rid of platform specific cpu clock configuration for AXS103 in
arch/arc/plat-axs10x/axs10x.c
* Add core pll node to AXS103 device tree to manage cpu frequency
* Refactor clock managment in arch/arc/plat-axs10x/axs10x.c
Eugeniy Paltsev (
HSDKv1 board manages its clocks using various PLLs. These PLL have same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.
Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed usin
