[PATCH v2 1/2] dt-bindings: Document the Synopsys DW AXI DMA bindings

This patch adds documentation of device tree bindings for the Synopsys DesignWare AXI DMA controller. Signed-off-by: Eugeniy Paltsev Acked-by: Rob Herring --- .../devicetree/bindings/dma/snps,axi-dw-dmac.txt | 34 ++ 1 file changed, 34 insertions(+) create mode 100644 Doc

[PATCH v2 2/2] dmaengine: Add DW AXI DMAC driver

This patch adds support for the DW AXI DMAC controller. DW AXI DMAC is a part of upcoming development board from Synopsys. In this driver implementation only DMA_MEMCPY and DMA_SG transfers are supported. Signed-off-by: Eugeniy Paltsev --- drivers/dma/Kconfig| 10 + drivers/d

[PATCH v2 0/2] dmaengine: Add DW AXI DMAC driver

This patch series add support for the DW AXI DMAC controller. DW AXI DMAC is a part of upcoming development board from Synopsys. In this driver implementation only DMA_MEMCPY and DMA_SG transfers are supported. Changes for v2: * Use async version of runtime PM get/put callbacks. * Use atomic_t

[PATCH] ARCv2: SLC: Make sure busy bit is set properly on SLC flushing

As reported in STAR 9001165532, an SLC control reg read (for checking busy state) right after SLC invalidate command may incorrectly return NOT busy causing software to NOT spin-wait while operation is underway. (and for some reason this only happens if L1 cache is also disabled - as required by IO