We were reading clock rate directly from device tree "clock-frequency"
property of corresponding clock node in show_cpuinfo function.
Such approach is correct only in case cpu is always clocked by
"fixed-clock". If we use clock driver that allows rate to be changed
this won't work as rate may chan
This patch series replaces reading device tree with getting CPU
clock frequency via clock driver in show_cpuinfo function.
In order to achieve this we also add cpu nodes to device tree which
describes SMP system and add "clocks" properties to all ARC cpu nodes.
Vlad Zakharov (3):
ARC: [dts] ad
ARC CPU cores are driven by core_clk so we add corresponding "clocks"
property to ARC cpu nodes.
Signed-off-by: Vlad Zakharov
---
arch/arc/boot/dts/skeleton.dtsi| 1 +
arch/arc/boot/dts/skeleton_hs.dtsi | 1 +
arch/arc/boot/dts/skeleton_hs_idu.dtsi | 1 +
3 files changed, 3 insertion
Trying to get clock for CPU cores on SMP systems I found that I was only
able to get clock for core[0]. That was because only one cpu@0 node was
represented in ARC HS device tree and it was impossible to get clock for
"non-existing" cores.
So as ARC HS may have up to 4 cores we update device tree
There is code duplicated over all architecture's headers for
futex_atomic_op_inuser. Namely op decoding, access_ok check for uaddr,
and comparison of the result.
Remove this duplication and leave up to the arches only the needed
assembly which is now in arch_futex_atomic_op_inuser.
Note that s390
This change adopts debugfs usage for outputting useful data.
As of today we print:
* Mode and real HW clock values
* Standard FB info
Code is heavily borrowed from ARM's HDLCD thus adding Liviu in Cc.
Signed-off-by: Alexey Brodkin
Cc: Liviu Dudau
Cc: Daniel Vetter
Cc: David Airlie
Cc: Jose
Hi Michael, Stephen,
On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> AXS10X boards manages it's clocks using various PLLs. These PLL has same
> dividers and corresponding control registers mapped to different addresses.
> So we add one common driver for such PLLs.
>
> Each PLL on AXS10X
Hi Daniel,
On Thu, 2017-03-02 at 20:54 +0100, Daniel Vetter wrote:
> On Thu, Mar 02, 2017 at 08:27:54PM +0300, Alexey Brodkin wrote:
> >
> > Since we cannot always generate exactly requested pixel clock
> > there's not much sense in checking requested_clock == clk_round_rate().
> > In that case f
On Fri, Mar 03, 2017 at 01:27:10PM +0100, Jiri Slaby wrote:
> There is code duplicated over all architecture's headers for
> futex_atomic_op_inuser. Namely op decoding, access_ok check for uaddr,
> and comparison of the result.
>
> Remove this duplication and leave up to the arches only the needed
On 3/3/2017 7:27 AM, Jiri Slaby wrote:
There is code duplicated over all architecture's headers for
futex_atomic_op_inuser. Namely op decoding, access_ok check for uaddr,
and comparison of the result.
Remove this duplication and leave up to the arches only the needed
assembly which is now in arc
We used to use "encoder-slave" property in PGU's
Device Tree node to refer to the encoder, but since there's
a way to find it with some code smarts we get rid of
obviously extra complication in PGU node.
Again inspired by ARM's HDLCD code.
Signed-off-by: Alexey Brodkin
Cc: Liviu Dudau
Cc: Danie
On Fri, Mar 03, 2017 at 03:30:35PM +0300, Alexey Brodkin wrote:
> This change adopts debugfs usage for outputting useful data.
> As of today we print:
> * Mode and real HW clock values
> * Standard FB info
>
> Code is heavily borrowed from ARM's HDLCD thus adding Liviu in Cc.
FWIW: Reviewed-by:
On Fri, Mar 03, 2017 at 06:19:24PM +0300, Alexey Brodkin wrote:
> We used to use "encoder-slave" property in PGU's
> Device Tree node to refer to the encoder, but since there's
> a way to find it with some code smarts we get rid of
> obviously extra complication in PGU node.
>
> Again inspired by
Hi Liviu,
On Fri, 2017-03-03 at 16:28 +, Liviu Dudau wrote:
> On Fri, Mar 03, 2017 at 06:19:24PM +0300, Alexey Brodkin wrote:
> >
> > - /* find the encoder node and initialize it */
> > - encoder_node = of_parse_phandle(drm->dev->of_node, "encoder-slave", 0);
> > - if (encoder_node) {
>
Hi Alexey,
On 03-03-2017 13:27, Alexey Brodkin wrote:
>
> So if I understood you correct here what I really need is just to get rid of
> existing check,
> right? I.e. the following is to be in v2 respin:
> --->8---
> diff --git a/drivers/gp
On Fri, Mar 03, 2017 at 05:48:19PM +, Alexey Brodkin wrote:
> Hi Liviu,
>
> On Fri, 2017-03-03 at 16:28 +, Liviu Dudau wrote:
> > On Fri, Mar 03, 2017 at 06:19:24PM +0300, Alexey Brodkin wrote:
> > >
> > > - /* find the encoder node and initialize it */
> > > - encoder_node = of_parse_pha
Hi Jose,
On Fri, 2017-03-03 at 18:05 +, Jose Abreu wrote:
> Hi Alexey,
>
>
> On 03-03-2017 13:27, Alexey Brodkin wrote:
> >
> >
> > So if I understood you correct here what I really need is just to get rid
> > of existing check,
> > right? I.e. the following is to be in v2 respin:
> > ---
On 03/03, Vlad Zakharov wrote:
> Hi Michael, Stephen,
>
> On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> > AXS10X boards manages it's clocks using various PLLs. These PLL has same
> > dividers and corresponding control registers mapped to different addresses.
> > So we add one common dr
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