[PATCH v3 0/3] Adding NPS400 drivers

From: Noam Camus Change Log-- v3 irqchip - Fix ARM build failure by adding missing include of linux/irq.h clocksource -- Avoid 64bit arch's to build driver by adding new dependency !PHYS_ADDR_T_64BIT This is since we use explicit io access of 32 bit. So for test

[PATCH v3 1/3] soc: Support for EZchip SoC

From: Noam Camus This header file is for NPS400 SoC. It includes macros for accessing memory mapped registers. These are functional registers that core can use to configure SoC. Signed-off-by: Noam Camus --- include/soc/nps/common.h | 150 ++ 1 file

[PATCH v3 2/3] clocksource: Add NPS400 timers driver

From: Noam Camus Add internal tick generator which is shared by all cores. Each cluster of cores view it through dedicated address. This is used for SMP system where all CPUs synced by same clock source. Signed-off-by: Noam Camus Cc: Daniel Lezcano Cc: Rob Herring Cc: Thomas Gleixner Cc: Joh

[PATCH v3 3/3] irqchip: add nps Internal and external irqchips

From: Noam Camus Adding EZchip NPS400 support. NPS internal interrupts are internally handled at Multi Thread Manager (MTM) that is signaled for deactivating an interrupt. External interrupts is handled also at Global Interrupt Controller (GIC) e.g. serial and network devices. Signed-off-by: Noa