[PATCH v4 00/19] Adding plat-eznps to ARC

2015-12-15 Thread Noam Camus
From: Noam Camus v4: 1) irqchip -- use irq_domain_add_linear() 2) clocksource -- use of_clk_get() 3) New header at include/soc use by platform and drivers 4) update DTS file for above fixed drivers v3: 1) irqchip: use MACROS instead of structures to decribe registers. 2) clocks

[PATCH v4 01/19] Documentation: Add EZchip vendor to binding list

2015-12-15 Thread Noam Camus
From: Noam Camus Add EZchip to vendor prefixes list. EZchip introduce the NPS platform for the ARC architecture. Signed-off-by: Noam Camus Acked-by: Rob Herring Cc: Pawel Moll --- Documentation/devicetree/bindings/arc/eznps.txt|7 +++ .../devicetree/bindings/vendor-prefixes.txt

[PATCH v4 02/19] soc: Support for EZchip SoC

2015-12-15 Thread Noam Camus
From: Noam Camus This header file is for NPS400 SoC. It includes macros for accessing memory mapped registers. These are functional registers that core can use to configure SoC. Signed-off-by: Noam Camus --- include/soc/nps/common.h | 123 ++ 1 file

[PATCH v4 04/19] clocksource: Add NPS400 timers driver

2015-12-15 Thread Noam Camus
From: Noam Camus Add internal tick generator which is shared by all cores. Each cluster of cores view it through dedicated address. This is used for SMP system where all CPUs synced by same clock source. Signed-off-by: Noam Camus Cc: Daniel Lezcano Cc: Rob Herring Cc: Thomas Gleixner Cc: Joh

[PATCH v4 03/19] ARC: [plat-eznps] define IPI_IRQ

2015-12-15 Thread Noam Camus
From: Noam Camus We add IPI irq definition to be used later by any irqchip such NPS400 IC. Signed-off-by: Noam Camus --- arch/arc/include/asm/irq.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h index 4fd7d62.

[PATCH v4 06/19] ARC: Set vmalloc size from configuration

2015-12-15 Thread Noam Camus
From: Noam Camus User space use lower 2G of the virtual address space. However kernel steals upper 512M of this space. This stolen space is used partially for vmalloc and the rest serves as gutter between kernel and user space. The vmalloc size is depend on NR_CPUS since "per cpu" mechanism use v

[PATCH v4 05/19] irqchip: add nps Internal and external irqchips

2015-12-15 Thread Noam Camus
From: Noam Camus Adding EZchip NPS400 support. NPS internal interrupts are internally handled at Multi Thread Manager (MTM) that is signaled for deactivating an interrupt. External interrupts is handled also at Global Interrupt Controller (GIC) e.g. serial and network devices. Signed-off-by: Noa

[PATCH v4 10/19] ARC: Add clock from device tree to time_init()

2015-12-15 Thread Noam Camus
From: Noam Camus External clock source can be used if included by one of DTS file of a chosen platform. Clocksource may be depend on some clk from DTS as the real source of this clock. Signed-off-by: Noam Camus Acked-by: Vineet Gupta --- arch/arc/kernel/time.c | 10 +- 1 files chang

[PATCH v4 07/19] ARC: rwlock: disable interrupts in !LLSC variant

2015-12-15 Thread Noam Camus
From: Noam Camus If we hold rwlock and interrupt occures we may end up spinning on it for ever during softirq. Note that this lock is an internal lock and since the lock is free to be used from any context, the lock needs to be IRQ-safe. Below you may see an example for interrupt we get while nl

[PATCH v4 08/19] ARC: rename smp operation init_irq_cpu() to init_per_cpu()

2015-12-15 Thread Noam Camus
From: Noam Camus This will better reflect its description i.e. "any needed setup..." and not just do an "IPI request". Signed-off-by: Noam Camus Acked-by: Vineet Gupta --- arch/arc/include/asm/smp.h |4 ++-- arch/arc/kernel/irq.c |4 ++-- arch/arc/kernel/mcip.c |2 +- arc

[PATCH v4 09/19] ARC: Mark secondary cpu online only after all HW setup is done

2015-12-15 Thread Noam Camus
From: Noam Camus In SMP setup, master loops for each_present_cpu calling cpu_up(). For ARC it returns as soon as new cpu's status becomes online, However secondary may still do HW initializing, machine or platform hook level. So turn secondary online only after all HW setup is done. Signed-off-b

[PATCH v4 11/19] ARC: [plat-eznps] Add eznps board defconfig and dts

2015-12-15 Thread Noam Camus
From: Noam Camus Adding default configuration file and DTS file Signed-off-by: Noam Camus --- arch/arc/boot/dts/eznps.dts| 93 arch/arc/configs/nps_defconfig | 85 2 files changed, 178 insertions(+), 0 deleti

[PATCH v4 13/19] ARC: [plat-eznps] Use dedicated user stack top

2015-12-15 Thread Noam Camus
From: Noam Camus NPS use special mapping right below TASK_SIZE. Hence we need to lower STACK_TOP so that user stack won't overlap NPS special mapping. Signed-off-by: Noam Camus Acked-by: Vineet Gupta --- arch/arc/include/asm/processor.h | 17 + arch/arc/mm/tlb.c

[PATCH v4 12/19] ARC: [plat-eznps] Add eznps platform

2015-12-15 Thread Noam Camus
From: Noam Camus This platform include boards: Hardware Emulator (HE) Simulator based upon nSIM. Signed-off-by: Noam Camus --- MAINTAINERS |6 + arch/arc/plat-eznps/Kconfig | 34 ++ arch/arc/plat-eznps/Makefile|7

[PATCH v4 15/19] ARC: [plat-eznps] Use dedicated SMP barriers

2015-12-15 Thread Noam Camus
From: Noam Camus NPS device got 256 cores and each got 16 HW threads (SMT). We use EZchip dedicated ISA to trigger HW scheduler of the core that current HW thread belongs to. This scheduling makes sure that data beyond barrier is available to all HW threads in core and by that to all in device (4

[PATCH v4 14/19] ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg

2015-12-15 Thread Noam Camus
From: Noam Camus We need our own implementaions since we lack LLSC support. Our extended ISA provided with optimized solution for all 32bit operations we see in these three headers. Signed-off-by: Noam Camus --- arch/arc/include/asm/atomic.h | 79 +++- arch/ar

[PATCH v4 16/19] ARC: [plat-eznps] Use dedicated identity auxiliary register.

2015-12-15 Thread Noam Camus
From: Noam Camus With generic "identity" num of CPUs is limited to 256 (8 bit). We use our alternative AUX register GLOBAL_ID (12 bit). Now we can support up to 4096 CPUs. Signed-off-by: Noam Camus --- arch/arc/include/asm/entry-compact.h |8 arch/arc/kernel/ctx_sw.c |

[PATCH v4 17/19] ARC: [plat-eznps] Use dedicated cpu_relax()

2015-12-15 Thread Noam Camus
From: Tal Zilcer Since the CTOP is SMT hardware multi-threaded, we need to hint the HW that now will be a very good time to do a hardware thread context switching. This is done by issuing the schd.rw instruction (binary coded here so as to not require specific revision of GCC to build the kernel)

[PATCH v4 19/19] ARC: Add eznps platform to Kconfig and Makefile

2015-12-15 Thread Noam Camus
From: Noam Camus This commit should be left last since only now eznps platform is in state which one can actually use. Signed-off-by: Noam Camus --- arch/arc/Kconfig |1 + arch/arc/Makefile |5 + 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/arc/Kconfig b/arch

[PATCH v4 18/19] ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE

2015-12-15 Thread Noam Camus
From: Noam Camus The default 256 bytes sometimes is just not enough. We usually provide earlycon=... and console=... and ip=... All this and more may need more room. Signed-off-by: Noam Camus Acked-by: Vineet Gupta --- arch/arc/include/asm/setup.h |4 1 files changed, 4 insertions(+)