On Thu, Sep 29, 2016 at 12:48:03PM -0700, Vineet Gupta wrote:
> > [1] There's an exception on 64-bit AMD CPUs because AMD blew it.
> > Also, x86 NMI return is itself severely overcomplicated because we don't
> > have good control over NMI nesting.
>
> For ARC (HS38 cores), there are 16 interrupt p
On 09/29/2016 11:54 AM, Andy Lutomirski wrote:
>> So lets first see how a single priority intr works on ARC (maybe on other
>> arches
>> > as well).
>> >
>> > 1. task t1 enters kernel syscall (Trap Exception on ARC), handler drops
>> > down to
>> > pure kernel model and proceeds into syscall hand
On Thu, Sep 29, 2016 at 9:47 AM, Vineet Gupta
wrote:
> On 09/28/2016 11:43 PM, Peter Zijlstra wrote:
>> On Wed, Sep 28, 2016 at 06:20:29PM -0700, Vineet Gupta wrote:
>>> On 09/28/2016 03:26 PM, Andy Lutomirski wrote:
>
>>
>>
>> userirq nmi
>>
>> |
>> |
>> `-> .
On Sep 28, 2016 6:20 PM, "Vineet Gupta" wrote:
>
> On 09/28/2016 03:26 PM, Andy Lutomirski wrote:
> >> Right, so what I think Vineet is asking is if we need to disable NMIs as
> >> > well, we cannot on x86 disable NMIs so no.
> >> >
> > The same argument works here, too: an NMI won't set TIF_NEED_
On 09/28/2016 11:43 PM, Peter Zijlstra wrote:
> On Wed, Sep 28, 2016 at 06:20:29PM -0700, Vineet Gupta wrote:
>> On 09/28/2016 03:26 PM, Andy Lutomirski wrote:
>
>
> userirq nmi
>
> |
> |
> `-> .
> |
> |
> |
>
On Wed, Sep 28, 2016 at 06:20:29PM -0700, Vineet Gupta wrote:
> On 09/28/2016 03:26 PM, Andy Lutomirski wrote:
> >> Right, so what I think Vineet is asking is if we need to disable NMIs as
> >> > well, we cannot on x86 disable NMIs so no.
> >> >
> > The same argument works here, too: an NMI won't s
On 09/28/2016 03:26 PM, Andy Lutomirski wrote:
>> Right, so what I think Vineet is asking is if we need to disable NMIs as
>> > well, we cannot on x86 disable NMIs so no.
>> >
> The same argument works here, too: an NMI won't set TIF_NEED_RESCHED
> without sending an IPI, so we can't miss a wakeup.
On Wed, Sep 28, 2016 at 3:44 PM, Vineet Gupta
wrote:
> On 09/28/2016 03:26 PM, Andy Lutomirski wrote:
>> 2. The low level return code, resume_user_mode_begin and/or
>> resume_kernel_mode
>> > > >> require interrupt safety, does that need to be NMI safe as well.
>> > > >> We ofcou
On 09/28/2016 03:26 PM, Andy Lutomirski wrote:
> 2. The low level return code, resume_user_mode_begin and/or
> resume_kernel_mode
> > > >> require interrupt safety, does that need to be NMI safe as well.
> > > >> We ofcourse want
> > > >> the very late register restore parts t
On Sep 28, 2016 1:37 PM, "Peter Zijlstra" wrote:
>
> On Wed, Sep 28, 2016 at 12:25:11PM -0700, Andy Lutomirski wrote:
> > > Yes. If the NMI returns to kernel space you must not attempt preemption
> > > for reasons you found :-),
> >
> > Last time I looked at this, I decided that there was no reaso
On Wed, Sep 28, 2016 at 12:25:11PM -0700, Andy Lutomirski wrote:
> > Yes. If the NMI returns to kernel space you must not attempt preemption
> > for reasons you found :-),
>
> Last time I looked at this, I decided that there was no reason that
> NMIs would ever need to handle preemption. Even if
On Wed, Sep 28, 2016 at 12:16 AM, Peter Zijlstra wrote:
> On Tue, Sep 27, 2016 at 05:22:13PM -0700, Vineet Gupta wrote:
>
>> > Yeah, Sparc64 might be a better example, it more closely matches your
>> > hardware. See
>> > arch/sparc/include/asm/irqflags_64.h:arch_local_irq_save().
>>
>> So I finall
On 09/28/2016 12:16 AM, Peter Zijlstra wrote:
>> 1. Is it OK in general to short-circuit preemption off irq checks for NMI
>> style
>> > interrupts.
> Yes. If the NMI returns to kernel space you must not attempt preemption
> for reasons you found :-), if the NMI returns to userspace you should do
On Tue, Sep 27, 2016 at 05:22:13PM -0700, Vineet Gupta wrote:
> > Yeah, Sparc64 might be a better example, it more closely matches your
> > hardware. See
> > arch/sparc/include/asm/irqflags_64.h:arch_local_irq_save().
>
> So I finally got around to doing this and as expected has turned out to be
Hi Peter,
On 11/17/2015 05:15 AM, Peter Zijlstra wrote:
> On Tue, Nov 17, 2015 at 06:23:21PM +0530, Vineet Gupta wrote:
>> On Tuesday 17 November 2015 05:55 PM, Peter Zijlstra wrote:
>>
>>> This is assuming you now have these NMIs we talked about earlier. If all
>>> you have are regular IRQs this
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