Hi Eugeniy,
On Fri, 2018-06-22 at 16:30 +0200, Eugeniy Paltsev wrote:
> Hi Vineet, Christoph,
> thanks for responding.
[snip]
> > > (BTW: current ARC dma_noncoherent_ops implementation also has same
> > > problem if IOC and HIGHMEM are enabled.)
> >
> > Can we highlight this fact, add error pri
Hi Vineet, Christoph,
thanks for responding.
On Mon, 2018-06-18 at 15:53 -0700, Vineet Gupta wrote:
> On 06/15/2018 05:58 AM, Eugeniy Paltsev wrote:
> > The ARC HS processor provides an IOC port (I/O coherency bus
> > interface) that allows external devices such as DMA devices
> > to access memory
On 06/15/2018 05:58 AM, Eugeniy Paltsev wrote:
> The ARC HS processor provides an IOC port (I/O coherency bus
> interface) that allows external devices such as DMA devices
> to access memory through the cache hierarchy, providing
> coherency between I/O transactions and the complete memory
> hierar
> +#ifndef ASM_ARC_DMA_MAPPING_H
> +#define ASM_ARC_DMA_MAPPING_H
> +
> +#define arch_setup_dma_ops arch_setup_dma_ops
> +
> +#include
> +
> +void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> + const struct iommu_ops *iommu, bool coherent);
Can you keep the
The ARC HS processor provides an IOC port (I/O coherency bus
interface) that allows external devices such as DMA devices
to access memory through the cache hierarchy, providing
coherency between I/O transactions and the complete memory
hierarchy.
Some recent SoC with ARC HS (like HSDK) allow to se
