On 04/04, Jose Abreu wrote:
> >> + fbdiv = i2s_pll_get_value(readl((void *)PLL_FBDIV_ADDR));
> >> + odiv = i2s_pll_get_value(readl((void *)PLL_ODIV0_ADDR));
> >> +
> >> + return (((clk->ref_clk / idiv ) * fbdiv) / odiv);
> > Again, too many parentheses. Also, any concerns of 32-bit
> > truncatio
Hi Stephen,
On 02-04-2016 02:02, Stephen Boyd wrote:
> On 03/31, Jose Abreu wrote:
>> arch/arc/boot/dts/axs10x_mb.dtsi | 5 ++
> Please remove this diff from this patch. dts changes go through
> non-clk trees.
Ok.
>
>> drivers/clk/Makefile | 1 +
>> drivers/clk/axs10x/Makef
On Thursday 31 March 2016 10:38 PM, Jose Abreu wrote:
> The ARC SDP I2S clock can be programmed using a
> specific PLL.
>
> This patch has the goal of adding a clock driver
> that programs this PLL.
>
> At this moment the rate values are hardcoded in
> a table but in the future it would be ideal
On 03/31, Jose Abreu wrote:
>
> arch/arc/boot/dts/axs10x_mb.dtsi | 5 ++
Please remove this diff from this patch. dts changes go through
non-clk trees.
> drivers/clk/Makefile | 1 +
> drivers/clk/axs10x/Makefile| 1 +
> drivers/clk/axs10x/i2s_pll_clock.c | 163
> ++
The ARC SDP I2S clock can be programmed using a
specific PLL.
This patch has the goal of adding a clock driver
that programs this PLL.
At this moment the rate values are hardcoded in
a table but in the future it would be ideal to
use a function which determines the PLL values
given the desired ra
