On Mon, 2018-02-26 at 18:42 +0200, Andy Shevchenko wrote:
> On Mon, Feb 26, 2018 at 4:56 PM, Eugeniy Paltsev
> wrote:
>
> > + chip->core_clk = devm_clk_get(chip->dev, "core-clk");
>
> Does the name come from datasheet?
>
> > + chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
>
On Mon, 2018-02-26 at 18:42 +0200, Andy Shevchenko wrote:
> On Mon, Feb 26, 2018 at 4:56 PM, Eugeniy Paltsev
> wrote:
> > +static int parse_device_properties(struct axi_dma_chip *chip)
> > +{
> > + ret = device_property_read_u32(dev, "snps,dma-masters", &tmp);
>
> Why it has prefix?
>
> >
On Mon, Feb 26, 2018 at 05:56:27PM +0300, Eugeniy Paltsev wrote:
> +/*
> + * Synopsys DesignWare AXI DMA Controller driver.
> + *
> + * Copyright (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
> + * Author: Eugeniy Paltsev
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
This needs to be in
On Mon, Feb 26, 2018 at 4:56 PM, Eugeniy Paltsev
wrote:
> This patch adds support for the DW AXI DMAC controller.
> DW AXI DMAC is a part of HSDK development board from Synopsys.
>
> In this driver implementation only DMA_MEMCPY transfers are
> supported.
> +/*
> + * Synopsys DesignWare AXI DMA C
This patch adds support for the DW AXI DMAC controller.
DW AXI DMAC is a part of HSDK development board from Synopsys.
In this driver implementation only DMA_MEMCPY transfers are
supported.
Signed-off-by: Eugeniy Paltsev
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MAINTAINERS|6 +
drivers/dma/Kconf
