Re: [PATCH v2 01/19] ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only

2021-08-16 Thread Vineet Gupta
On 8/15/21 2:27 AM, Mike Rapoport wrote: On Thu, Aug 12, 2021 at 04:37:35PM -0700, Vineet Gupta wrote: MMU SCRATCH_DATA0 register is intended to cache task pgd. However in ARC700 SMP port, it has to be repurposed for reentrant interrupt handling, while UP port doesn't. We currently ahandle boe

Re: [PATCH v2 01/19] ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only

2021-08-15 Thread Mike Rapoport
On Thu, Aug 12, 2021 at 04:37:35PM -0700, Vineet Gupta wrote: > MMU SCRATCH_DATA0 register is intended to cache task pgd. However in > ARC700 SMP port, it has to be repurposed for reentrant interrupt > handling, while UP port doesn't. We currently ahandle boe usecases

[PATCH v2 01/19] ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only

2021-08-12 Thread Vineet Gupta
MMU SCRATCH_DATA0 register is intended to cache task pgd. However in ARC700 SMP port, it has to be repurposed for reentrant interrupt handling, while UP port doesn't. We currently ahandle boe usecases using a fabricated which has usual issues of dependency nesting and ugliness. So clean this up: