On Tue, Sep 04, 2018 at 09:34:43PM +, Vineet Gupta wrote:
> Sorry I missed that request of yours on top of the last msg. I would really
> want
> this to get into 4.19 (understand that merge window is done etc) given that
> there's a bunch of other changes lined up behind this one. I was just s
On 09/04/2018 02:07 PM, Christoph Hellwig wrote:
> On Tue, Sep 04, 2018 at 01:14:49PM -0700, Vineet Gupta wrote:
>> Apologies for the delay in getting to this - series applied and pushed to
>> for-curr
> This is going to create really annoying merge conflicts with
> work pending for the dma-mappin
On Tue, Sep 04, 2018 at 01:14:49PM -0700, Vineet Gupta wrote:
> Apologies for the delay in getting to this - series applied and pushed to
> for-curr
This is going to create really annoying merge conflicts with
work pending for the dma-mapping tree. That's why I requested earlier
to merge it eith
On 07/30/2018 09:26 AM, Eugeniy Paltsev wrote:
> The ARC HS processor provides an IOC port (I/O coherency bus
> interface) that allows external devices such as DMA devices
> to access memory through the cache hierarchy, providing
> coherency between I/O transactions and the complete memory
> hierar
On 08/13/2018 10:27 AM, Eugeniy Paltsev wrote:
>> You didn't pay attention to my previous comment on this !
>> IOC port can be considered a micro-architecture optimization (an important
>> one
>> though). The main thing is hardware snooping DMA transactions which enabled
>> IOC in
>> first place.
On Mon, 2018-08-13 at 16:19 +, Vineet Gupta wrote:
> On 07/30/2018 09:26 AM, Eugeniy Paltsev wrote:
> > The ARC HS processor provides an IOC port (I/O coherency bus
> > interface) that allows external devices such as DMA devices
> > to access memory through the cache hierarchy, providing
> > co
On 07/30/2018 09:26 AM, Eugeniy Paltsev wrote:
> The ARC HS processor provides an IOC port (I/O coherency bus
> interface) that allows external devices such as DMA devices
> to access memory through the cache hierarchy, providing
> coherency between I/O transactions and the complete memory
> hierar
The ARC HS processor provides an IOC port (I/O coherency bus
interface) that allows external devices such as DMA devices
to access memory through the cache hierarchy, providing
coherency between I/O transactions and the complete memory
hierarchy.
Some recent SoC with ARC HS (like HSDK) allow to se
