On Tue, 2017-08-22 at 13:45 -0700, Vineet Gupta wrote:
> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> > Add core pll node (core_clk) to manage cpu frequency.
> > core_clk represents pll itself.
> > input_clk represents clock signal source (basically xtal) which
> > comes to pll input.
> >
> >
On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/axc003.dtsi | 11 ++
On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/axc003.dtsi | 11 ++
Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/axc003.dtsi | 11 +--
arch/arc/boot/dts/axc003_idu.dtsi | 11
