On Wed, Nov 27, 2019 at 11:01:23AM +0300, Alexey Brodkin wrote:
> 8-letter strings representing ARC perf events are stores in two
> 32-bit registers as ASCII characters like that: "IJMP", "IALL", "IJMPTAK" etc.
>
> And the same order of bytes in the word is used regardless CPU endianness.
>
> Whi
kernel.org
> Subject: Re: [PATCH] ARC: perf: Accommodate big-endian CPU
>
> On Tue, Nov 05, 2019 at 07:52:16PM +, Alexey Brodkin wrote:
> > Hi Sasha, Greg,
> >
> > > -Original Message-
> > > From: Sasha Levin
> > > Sent: Saturday, October 26,
8-letter strings representing ARC perf events are stores in two
32-bit registers as ASCII characters like that: "IJMP", "IALL", "IJMPTAK" etc.
And the same order of bytes in the word is used regardless CPU endianness.
Which means in case of big-endian CPU core we need to swap bytes to get
the sam
a...@lists.infradead.org
> > Cc: linux-ker...@vger.kernel.org; sta...@vger.kernel.org;
> > sta...@vger.kernel.org
> > Subject: Re: [PATCH] ARC: perf: Accommodate big-endian CPU
> >
> > Hi,
> >
> > [This is an automated email]
> >
> > This commit has b
rg
> Subject: Re: [PATCH] ARC: perf: Accommodate big-endian CPU
>
> Hi,
>
> [This is an automated email]
>
> This commit has been processed because it contains a -stable tag.
> The stable tag indicates that it's relevant for the following trees: all
>
> The bot
Hi,
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.3.7, v4.19.80, v4.14.150, v4.9.197,
v4.4.197.
v5.3.7: Build OK!
v4.19.80: Faile
8-letter strings representing ARC perf events are stores in two
32-bit registers as ASCII characters like that: "IJMP", "IALL", "IJMPTAK" etc.
And the same order of bytes in the word is used regardless CPU endianness.
Which means in case of big-endian CPU core we need to swap bytes to get
the sam
