Quoting Peter Zijlstra (2023-01-12 11:43:55)
> OMAP was the one and only user.
>
> Signed-off-by: Peter Zijlstra (Intel)
> Reviewed-by: Ulf Hansson
> Acked-by: Rafael J. Wysocki
> Acked-by: Frederic Weisbecker
> Tested-by: Tony Lindgren
> Tested-by: Ulf Hansson
>
Quoting Eugeniy Paltsev (2020-03-11 06:41:15)
> Add support for 148.5MHz clock for HDMI PLL
>
> Signed-off-by: Eugeniy Paltsev
> ---
Applied to clk-next
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Quoting Eugeniy Paltsev (2020-03-11 06:41:14)
> Support setting PLL to bypass mode to support output frequency
> equal to input one.
>
> Signed-off-by: Eugeniy Paltsev
> ---
Applied to clk-next
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Quoting Eugeniy Paltsev (2020-03-11 06:41:13)
> If PLL is bypassed the EN (enable) bit has no effect on
> output clock.
>
> Signed-off-by: Eugeniy Paltsev
> ---
Applied to clk-next
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htt
Quoting Geert Uytterhoeven (2020-02-12 02:00:47)
> The ARC platform code is not a clock provider, and just needs to call
> of_clk_init().
>
> Hence it can include instead of .
>
> Signed-off-by: Geert Uytterhoeven
> ---
Revi
pll output frequency
> ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
> ARC: [plat-axs103]: Set initial core pll output frequency
> ARC: [plat-axs103] refactor the quad core DT quirk code
>
Patches look good to me.
Acked-by: Stephen Boyd
--
Qualcomm Inn
On 08/25, Eugeniy Paltsev wrote:
> HSDK board manages its clocks using various PLLs. These PLL have same
> dividers and corresponding control registers mapped to different addresses.
> So we add one common driver for such PLLs.
>
> Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
On 07/14, Eugeniy Paltsev wrote:
> HSDKv1 boards manages it's clocks using various PLLs. These PLL has same
s/it's/its/
s/has/have/
> dividers and corresponding control registers mapped to different addresses.
> So we add one common driver for such PLLs.
>
> Each PLL on HSDK board consist of th
On 07/27, Vineet Gupta wrote:
> Hi Stephen,
>
> On 07/14/2017 09:01 PM, Eugeniy Paltsev wrote:
> >HSDKv1 boards manages it's clocks using various PLLs. These PLL has same
> >dividers and corresponding control registers mapped to different addresses.
> >So we add one common driver for such PLLs.
>
On 06/21, Eugeniy Paltsev wrote:
> AXS10X boards manages it's clocks using various PLLs. These PLL has same
> dividers and corresponding control registers mapped to different addresses.
> So we add one common driver for such PLLs.
>
> Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV
On 04/21, Vlad Zakharov wrote:
> diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c
> new file mode 100644
> index 000..e242df0
> --- /dev/null
> +++ b/drivers/clk/axs10x/pll_clock.c
> @@ -0,0 +1,334 @@
> +/*
> + * Synopsys AXS10X SDP Generic PLL clock driver
> + *
> +
On 02/21, Vlad Zakharov wrote:
> diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
> b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
> new file mode 100644
> index 000..5706246
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
> >
> > Acked-by: Rob Herring
> > Signed-off-by: Vlad Zakharov
> > Signed-off-by: Jose Abreu
> > Cc: Michael Turquette
> > Cc: Stephen Boyd
> > Cc: Mark Rutland
>
> Maybe you have any comments or remarks about this patch? And if you don't
&
On 05/02, Jose Abreu wrote:
> The ARC SDP I2S clock can be programmed using a
> specific PLL.
>
> This patch has the goal of adding a clock driver
> that programs this PLL.
>
> At this moment the rate values are hardcoded in
> a table but in the future it would be ideal to
> use a function which
On 04/19, Jose Abreu wrote:
>
> @Stephen: can you give some input so that I can submit a v6?
>
I don't prefer putting the second register in the same DT node,
but that's really up to the DT reviewers to approve such a
design. The current binding has been acked by Rob right?
Assuming the new bin
On 04/04, Jose Abreu wrote:
> >> + fbdiv = i2s_pll_get_value(readl((void *)PLL_FBDIV_ADDR));
> >> + odiv = i2s_pll_get_value(readl((void *)PLL_ODIV0_ADDR));
> >> +
> >> + return (((clk->ref_clk / idiv ) * fbdiv) / odiv);
> > Again, too many parentheses. Also, any concerns of 32-bit
> > truncatio
On 04/11, Jose Abreu wrote:
> new file mode 100644
> index 000..3ba4e2f
> --- /dev/null
> +++ b/drivers/clk/axs10x/i2s_pll_clock.c
> @@ -0,0 +1,217 @@
> +
> +static int i2s_pll_clk_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node
On 03/31, Jose Abreu wrote:
>
> arch/arc/boot/dts/axs10x_mb.dtsi | 5 ++
Please remove this diff from this patch. dts changes go through
non-clk trees.
> drivers/clk/Makefile | 1 +
> drivers/clk/axs10x/Makefile| 1 +
> drivers/clk/axs10x/i2s_pll_clock.c | 163
> ++
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