>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
>Sent: Monday, August 21, 2017 20:04 PM
>> +
>> +/* Handle an out of bounds mtm hs counter value */ static void __init
>> +handle_mtm_hs_ctr_out_of_bounds_error(uint8_t val) {
>> +pr_err("** The value must be in range [%d,%d] (inclu
From: Noam Camus
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig| 27
arch/arc
that implement a different set of auxiliary registers
disabling this configuration insures that we initialize registers on
every cpu and not just for the first thread of the core.
Example for non shared registers is working with EZsim (non silicon)
Signed-off-by: Liav Rehana
Signed-off-by: Noam
From: Noam Camus
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HW scheduler.
Signed-off-by: Noam Camus
---
Documentation/admin-guide/kernel
From: Noam Camus
Now it can be hidden by passing higher loglevel sevirity at cmdline
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
: Elad Kanfi
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/include/plat/ctop.h |1 +
arch/arc/plat-eznps/mtm.c | 12
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h
b/arch/arc/plat-eznps/include/plat
d-off-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h | 24
arch/arc/include/asm/ptrace.h|5 +
arch/arc/kernel/process.c|4
3 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/entry-compact.h
b
From: Noam Camus
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. address range of node0 assumed
From: Noam Camus
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while
From: Noam Camus
Change Log:
V2 -> V3
1) turn ARC prink's into pr_info as suggested by Vineet
2) For new command line argument (hs counter) shorten error massage to a single
line,
again as Vineet commented.
V1 -> V2
1) I added "Handle memory error as an exception" pa
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
From: Noam Camus
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once local_irq_enable() called can hit another one before we
managed to restore last one and pop
From: Noam Camus
This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096
For the extreme case like in eznps platform We use
all gutter between kernel and user.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig | 11 +++
arch/arc/include/asm/highmem.h |8
From: Noam Camus
This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096
For the extreme case like in eznps platform We use
all gutter between kernel and user.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig | 11 +++
arch/arc/include/asm/highmem.h |8
From: Noam Camus
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig| 27
arch/arc
d-off-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h | 24
arch/arc/include/asm/ptrace.h|5 +
arch/arc/kernel/process.c|4
3 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/entry-compact.h
b
From: Noam Camus
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once local_irq_enable() called can hit another one before we
managed to restore last one and pop
: Elad Kanfi
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/include/plat/ctop.h |1 +
arch/arc/plat-eznps/mtm.c | 12
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h
b/arch/arc/plat-eznps/include/plat
From: Noam Camus
Chanlog:
V1 -> V2
1) I added "Handle memory error as an exception" patch from previous set
It now turn do_memory_error() into weak sybol.
It is then overriden by NPS400 platform, to simply call die().
2) This set is now based on arc-next branch
Summary:
With t
From: Noam Camus
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HE scheduler.
Signed-off-by: Noam Camus
---
Documentation/admin-guide/kernel
From: Noam Camus
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. address range of node0 assumed
From: Noam Camus
On ARC700, user mode memory error is treated as L2 interrupt, but NPS
hardware treats it as Machine Check exception.
Address this by defining an NPS specific bus error handler.
Signed-off-by: Noam Camus
Signed-off-by: Elad Kanfi
---
arch/arc/kernel/traps.c |2
From: Noam Camus
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while
platforms that implement a different set of auxiliary registers
there is a need to initialize them on every cpu and not just the for the
first thread of the core.
Signed-off-by: Liav Rehana
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/Kconfig | 11 +++
arch/arc/plat-eznps/entry.S |2
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
From: Noam Camus
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus
---
arch/arc/kernel/setup.c |6
From: Noam Camus
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once local_irq_enable() called can hit another one before we
managed to restore last one and pop
From: Noam Camus
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus
---
arch/arc/kernel/setup.c |6
: Elad Kanfi
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/include/plat/ctop.h |1 +
arch/arc/plat-eznps/mtm.c | 12
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h
b/arch/arc/plat-eznps/include/plat
From: Noam Camus
With this patch set I continue the effort of upstreaming the eznps platform for
arch/arc.
It comprise of couple of patches from last set yet not accepted,
patches for HW erratas and some misc extensions such for HIGHMEM / NUMA.
This set got more generic ARC changes than
From: Noam Camus
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. address range of node0 assumed
From: Noam Camus
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while
d-off-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h | 24
arch/arc/include/asm/ptrace.h|5 +
arch/arc/kernel/process.c|4
3 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/entry-compact.h
b
From: Noam Camus
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HE scheduler.
Signed-off-by: Noam Camus
---
Documentation/admin-guide/kernel
From: Noam Camus
This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096
For the extreme case like in eznps platform We use
all gutter between kernel and user.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig | 11 +++
arch/arc/include/asm/highmem.h |8
From: Noam Camus
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig| 27
arch/arc
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
platforms that implement a different set of auxiliary registers
there is a need to initialize them on every cpu and not just the for the
first thread of the core.
Signed-off-by: Liav Rehana
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/Kconfig | 11 +++
arch/arc/plat-eznps/entry.S |2
> From: Noam Camus
> Sent: Wednesday, June 7, 2017 9:08 AM
>To: 'Vineet Gupta' ;
>linux-snps-arc@lists.infradead.org
>Cc: linux-ker...@vger.kernel.org; Elad Kanfi
>Subject: RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an
>exception
>>
>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
>Sent: Wednesday, June 7, 2017 1:11 AM
...
>> +
>> +config EZNPS_MEM_ERROR
>> + bool "ARC-EZchip Memory error as an exception"
>> + depends on ARC_PLAT_EZNPS
>> + default n
>So you set default to "n" - thus by default it wo
> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
> Sent: Friday, June 2, 2017 21:36 PM
...
>> arch/arc/include/asm/spinlock.h |6 ++
>> 1 files changed, 6 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arc/include/asm/spinlock.h
>> b/arch/arc/include/asm/spinlock.h ind
> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
> Sent: Friday, June 2, 2017 22:04 PM
>> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
>> index feaa471..c5f946c 100644
>> --- a/arch/arc/plat-eznps/Kconfig
>> +++ b/arch/arc/plat-eznps/Kconfig
>> @@ -32,3 +32,14 @
From: Noam Camus
Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.
Signed-off-by: Noam Camus
---
arch/arc/mm/tlbex.S |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm
From: Noam Camus
When HW threads are active we want CPU to enter idle state only
for the calling HW thread and not to put on sleep all HW threads
sharing this core. For this need the NPS400 got dedicated instruction
so only calling thread is entring sleep and all other are still awake
and can
From: Noam Camus
This way when we execute "ex" during trying to hold lock we can switch to
other HW thread and utilize the core intead of just spinning on a lock.
We noticed about 10% improvement of execution time with hackbench test.
Signed-off-by: Noam Camus
---
arch/arc/i
From: Noam Camus
For User Mode Memory Bus Error some platforms do not creat interrupt
level 2 e.g. nps400 creates machine check exception.
Turning mem_service into weak symbol allows each platform to override
mem_service with its own implementation.
Signed-off-by: Noam Camus
---
arch/arc
From: Noam Camus
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus
---
arch/arc/kernel/setup.c |6
From: Liav Rehana
Signed-off-by: Liav Rehana
Signed-off-by: Noam Camus
Reviewed-by: Alexey Brodkin
---
arch/arc/mm/fault.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 162c975..a0b7bd6 100644
--- a/arch/arc/mm
From: Noam Camus
This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
If set, it will cause the kernel to handle user memory error
as a machine check exception.
It is required in order to align the NPS simulator memory
error handling to the one of the NPS400 real chip behavior.
We override
From: Liav Rehana
Signed-off-by: Liav Rehana
Signed-off-by: Noam Camus
Reviewed-by: Alexey Brodkin
---
arch/arc/kernel/entry-compact.S | 22 +++---
1 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry
From: Noam Camus
This counter represents threshold for consecutive stall that which
trigger HW threads scheduling.
When this feature is enabled low values of this counter cause
downgrade in performance and in the worst case even a livelock.
Remove those couple of lines and resort to HW reset
From: Noam Camus
Change Log
---
v1 --> v2:
Outcome of Alexey Brodkin comments
1) Turned mem_service into weak symbol, so it can be override
by any platform
2) remove ifedf wrapper on '88' lable at assembly of TLB exception.
With this patch set I continue the effort of up
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
From: Noam Camus
Signed-off-by: Noam Camus
Reviewed-by: Alexey Brodkin
---
arch/arc/plat-eznps/Kconfig |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 1595a38..feaa471 100644
--- a/arch/arc/plat-eznps
>From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com]
>Sent: Thursday, May 25, 2017 14:31 PM
...
>> > Why don't you just make simulator behaving exactly as your real chip?
>> I can't change simulator core behavior. nSIM is a Synopsys proprietary code.
>Well probably it worth discussing with
> From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com]
> Sent: Thursday, May 25, 2017 14:15 PM
>>
>> diff --git a/arch/arc/kernel/entry-compact.S
>> b/arch/arc/kernel/entry-compact.S index f285dbb..d152d36 100644
>> --- a/arch/arc/kernel/entry-compact.S
>> +++ b/arch/arc/kernel/entry-compa
>From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com]
>Sent: Thursday, May 25, 2017 14:10 PM
...
>> diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
>> index ffd..e0cb36b 100644
>> --- a/arch/arc/plat-eznps/mtm.c
>> +++ b/arch/arc/plat-eznps/mtm.c
>> @@ -119,8 +119,6 @@
>From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com]
>Sent: Thursday, May 25, 2017 14:01 PM
...
>> /* Get free TLB slot: Set = computed from vaddr, way = random */
>> sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
>>
>> @@ -287,6 +294,9 @@ ex_saved_reg1:
>> #else
>> sr TLBInsertEnt
From: Liav Rehana
Signed-off-by: Liav Rehana
Signed-off-by: Noam Camus
---
arch/arc/mm/fault.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 162c975..a0b7bd6 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
From: Noam Camus
This counter represents threshold for consecutive stall that which
trigger HW threads scheduling.
Low values of this counter cause downgrade in performance
and in the worst case even a livelock.
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/mtm.c |2 --
1 files
From: Noam Camus
Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.
Signed-off-by: Noam Camus
---
arch/arc/mm/tlbex.S | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
From: Noam Camus
This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
If set, it will cause the kernel to handle user memory error
as a machine check exception.
It is required in order to align the NPS simulator memory
error handling to the one of the NPS400 real chip behavior.
Signed-off
From: Noam Camus
When HW threads are active we want CPU to enter idle state only
for the calling HW thread and not to put on sleep all HW threads
sharing this core. For this need the NPS400 got dedicated instruction
so only calling thread is entring sleep and all other are still awake
and can
From: Liav Rehana
Signed-off-by: Liav Rehana
Signed-off-by: Noam Camus
---
arch/arc/kernel/entry-compact.S | 22 +++---
1 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index 9211707..f285dbb
From: Noam Camus
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/Kconfig |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 1595a38..feaa471 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat
From: Noam Camus
This way when we execute "ex" during trying to hold lock we can switch to
other HW thread and utilize the core intead of just spinning on a lock.
We noticed about 10% improvement of execution time with hackbench test.
Signed-off-by: Noam Camus
---
arch/arc/i
From: Noam Camus
With this patch set I continue the effort of upstreaming the
eznps platform for arch/arc.
it combine of patches for typos and other for HW erratas and some
for performance.
All selected as ones that may be obvious for merge with arc next.
This was based on for-curr branch as
From: Noam Camus
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus
---
arch/arc/kernel/setup.c |6
From: Noam Camus
Make ATOMIC_INIT available for all ARC platforms (including plat-eznps)
Signed-off-by: Noam Camus
---
arch/arc/include/asm/atomic.h |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h
index
It is OK.
Please remove.
Noam
-Original Message-
From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
Sent: Wednesday, February 1, 2017 10:56 PM
To: Noam Camus
Cc: arcml
Subject: Need for ARC_HAS_COH_CACHES
Hi Noam,
When we started off with NPS support, it seems dcache was not
From: Noam Camus
Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to
From: Noam Camus
Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to
From: Noam Camus
nps_setup_clocksource() should take node as only argument as defined by
typedef int (*of_init_fn_1_ret)(struct device_node *)
Therefore need to replace:
int __init nps_setup_clocksource(struct device_node *node, struct clk *clk)
with
int __init nps_setup_clocksource(struct
From: Noam Camus
Change log
---
V6 --> V7
Apply several comments made by Daniel Lezcano:
1) Remove CLOCK_EVT_FEAT_PERIODIC support. This way it is
pure oneshot driver. This simplifies driver so that:
nps_clkevent_add_thread()
nps_clkevent_rm_thread()
are more clearer without any vague lo
From: Noam Camus
This new header file is for NPS400 SoC (part of ARC architecture).
The header file includes macros for save/restore of HW scheduling.
The control of HW scheduling is achieved by writing core registers.
This code was moved from arc/plat-eznps so it can be used
from drivers
> From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com]
> Sent: Tuesday, November 8, 2016 4:08 PM
>Could you please provide a changelog (v1 -> v2) so reviewers may have a hint
>about changes you made if any.
... Just fix some typos in log
This line somehow was removed from patch while sendin
From: Noam Camus
For CONFIG_SERIAL_EARLYCON we need 800MHz for NPS SoC
The early console driver uses BASE_BAUD and not using dtb.
The default of 50MHz is NOT good for NPS SoC.
Signed-off-by: Noam Camus
---
arch/arc/kernel/devtree.c |2 ++
1 files changed, 2 insertions(+), 0 deletions
From: Noam Camus
For CONFIG_SERIAL_EARLYCON we need 800MHz for NPS SoC
The early console driver uses BASE_BAUD (and not using dtb) and
default of 50MHz is good for NPS SoC.
Signed-off-by: Noam Camus
---
arch/arc/kernel/devtree.c |2 ++
1 files changed, 2 insertions(+), 0 deletions
From: Noam Camus
Today we register to plat_smp_ops.clear() method which actually
is acking the IPI.
However this is already taking care by our irqchip driver specifically
by the irq_chip.irq_eoi() method.
This is perfect timing where it should be done and no special handling
is needed at
> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
> Sent: Tuesday, November 8, 2016 9:21 AM
>I'm planning to merge this valid patch. Please look at arc mailing list for
>more context !
>Can you please check if this doesn't break ur platform and/or requires a fixup.
Ack by me
-Noam
__
From: Noam Camus
Generic IRQ mechanism is already acknowledge the IPI IRQ.
Doing this once more time in IPI handler is not needed.
Signed-off-by: Noam Camus
---
arch/arc/plat-eznps/smp.c |6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/arch/arc/plat-eznps/smp.c b
>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
>Sent: Tuesday, November 1, 2016 12:48 AM
>ARC timers use aux registers for programming and this paves way for moving ARC
>timer drivers into drivers/clocksource
Maybe in this patch or just another one could you move from timer.c to the ne
From: Noam Camus
At smp_prepare_cpus() we set present cpu mask as part of init
for all CPUs at range [0-max_cpus].
This is done without checking if this mask is already being set.
At platform of eznps this mask is already being initialized at
smp_init_cpus() by using hook
From: Noam Camus
Today we use smp_init_cpus() to set cpu possible mask
and we use smp_prepare_cpus() to set cpu present mask.
For possible mask we use all CPUs at range [0-NR_CPUS] and
for present mask we use all CPUs at range [0-max_cpus]
which is actually the same as possible mask (no hutplug
From: Noam Camus
num_possible_cpus() returns how many CPUs may be present on system.
However we want the highest possible CPU number.
This may be differ in a sparsed possible CPUs map.
Such map achived by OF for plat-eznps.
For example if we have:
possible cpus mask 0,3
Then:
num_possible_cpus
> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
> Sent: Tuesday, October 18, 2016 8:49 PM
>>
>> num_possible_cpus() returns how many CPUs may be present on system.
>> However we want the highest possible CPU number.
>
>Highest possible number "Detected" at boot ? Can you explain a bit mo
From: Noam Camus
num_possible_cpus() returns how many CPUs may be present on system.
However we want the highest possible CPU number.
This may be differ in a sparsed possible CPUs map.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/kernel/setup.c |2 +-
1 files changed, 1
From: Noam Camus
Seem like values assigned as absolute number and not and
shift value, i.e. should be 0 for one node (2^0) and 1 for
couple of nodes (2^1)
Signed-off-by: Noam Camus
---
arch/arc/Kconfig |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arc
From: Noam Camus
Build brekeage since last changes to generic atomic operations.
Added couple of missing macros which are now mandatory
Signed-off-by: Noam Camus
---
arch/arc/include/asm/atomic.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm
>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com]
>Sent: Tuesday, June 28, 2016 11:32 AM
>> I noticed that arc-timer driver appears twice in DTS file so first one
>> will invoke initialization of clockevent and second the clocksource.
>> Please note that both update same global variable a
nps_timer_init);
> +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
> +nps_timer_init);
> diff --git a/drivers/clocksource/timer-oxnas-rps.c
> b/drivers/clocksource/timer-oxnas-rps.c
> index 0d99f40..bd887e2 100
Hi Marc,
Could you review this patch, this is last one of this set which needs ack.
This patch set is out there long time and I will appreciate any feedback.
Regards,
Noam
From: linux-snps-arc on behalf of
Noam Camus
Sent: Sunday, April 3, 2016 9:14 PM
>From: Daniel Lezcano
>Sent: Thursday, April 7, 2016 7:57 PM
>> Add internal tick generator which is shared by all cores.
>> Each cluster of cores view it through dedicated address.
>> This is used for SMP system where all CPUs synced by same
>> clock source.
>Acked-by: Daniel Lezcano
Thank yo
From: Noam Camus
Change Log--
v8:
Change macro name from IPI_IRQ to NPS_IPI_IRQ.
This was needed due to build warning when building for parsic.
v7:
Rebased on latest HEAD (4.6-rc1)
Added change log to all patches to ease review.
v6:
Files headers changed to start with:
Copyright (c) 2016
From: Noam Camus
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Vineet Gupta
---
v8:
Change macro name from IPI_IRQ to
From: Noam Camus
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Rob Herring
Cc: Thomas Gleixner
Cc
From: Noam Camus
Adding EZchip NPS400 support.
Internal interrupts are handled by Multi Thread Manager (MTM)
Once interrupt is serviced MTM is acked for deactivating the interrupt.
External interrupts are handled by MTM as well as at Global Interrupt
Controller (GIC) e.g. serial and network
From: Noam Camus
Change Log--
v7:
Rebased on latest HEAD (4.6-rc1)
Added change log to all patches to ease review.
v6:
Files headers changed to start with:
Copyright (c) 2016, Mellanox Technologies
...
This is due to the acquisition of EZchip made by Mellanox.
One can still find "EZchip&
From: Noam Camus
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Rob Herring
Cc: Thomas Gleixner
Cc
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